Motorola DSP56009 User Manual page 174

Serial Host Interface
SHI Programming Considerations
The HREQ input pin is ignored by the SPI master device if the HRQE[1:0] bits are
cleared, and considered if any of them is set. When asserted by the slave device,
HREQ indicates that the external slave device is ready for the next data transfer. As a
result, the SPI master sends clock pulses for the full data word transfer. HREQ is
deasserted by the external slave device at the first clock pulse of the new data
transfer. When deasserted, HREQ will prevent the clock generation of the next data
word transfer until it is asserted again. Connecting the HREQ line between two
SHI-equipped DSPs, one operating as an SPI master device and the other as an SPI
slave device, enables full hardware handshaking if CPHA = 1. For CPHA = 0, HREQ
should be disabled by clearing HRQE[1:0].
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5.6.3 I C Slave Mode
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The I C Slave mode is entered by enabling the SHI (HEN = 1), selecting the I
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(HI C = 1), and selecting the Slave mode of operation (HMST = 0). In this operational
mode the contents of HCKR are ignored. When configured in the I
SHI external pins operate as follows:
• SCK/SCL is the SCL serial clock input.
• MISO/SDA is the SDA open drain serial data line.
• MOSI/HA0 is the HA0 slave device address input.
• SS/HA2 is the HA2 slave device address input.
• HREQ is the Host Request output.
When the SHI is enabled and configured in the I
inspects the SDA and SCL lines to detect a Start event. Upon detection of the Start
event, the SHI receives the slave device address byte and enables the slave device
address recognition unit. If the slave device address byte was not identified as its
personal address, the SHI controller will fail to acknowledge this byte by not driving
low the SDA line at the ninth clock pulse (ACK = 1). However, it continues to poll the
SDA and SCL lines to detect a new Start event. If the personal slave device address
was correctly identified, the slave device address byte is acknowledged (ACK = 0 is
sent) and a receive/transmit session is initiated according to the eighth bit of the
received slave device address byte (i.e., the R/W bit).
5.6.3.1 Receive Data in I
A receive session is initiated when the personal slave device address has been
correctly identified and the R/W bit of the received slave device address byte has
been cleared. Following a receive initiation, data in the SDA line is shifted into IOSR
MSB first. Following each received byte, an acknowledge (ACK = 0) is sent at the
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C Slave Mode
DSP56009 User's Manual
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C Slave mode, the
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C Slave mode, the SHI controller
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C mode
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