Table 4-14 Word-Address-To-Physical-Address Mapping For Dram - Motorola DSP56009 User Manual

External Memory Interface
EMI Address Generation
low-logic level. Device select pins are deasserted. Table 4-14 describes the
word-address-to-physical-address mapping for DRAM. Table 4-15 on page 4-29
summarizes the address generation for DRAM relative addressing.

Table 4-14 Word-Address-to-Physical-Address Mapping for DRAM

EAM DRAM ROW/
[2:0] size COL
100 64 K R
C
C
C
C
C
C
101 256 K R
C
C
C
C
C
C
110 1 M R
C
C
C
C
C
C
111 4 M R
C
C
C
C
C
C
4-28
EWL
EBW MA10 MA9 MA8 MA7 MA[6:3] MA2 MA1 MA0
[1:0]
00 0 0
0
1 0
01 0 0
1 0
1X 0 0
1 0
00 0 0
0
1 0
01 0 0
1 0
1X 0 0
1 0
00 0 0
0 A18 A17
1 0 A19 A18
01 0 0 A17 A16
1 0 A18 A17
1X 0 0 A16 A15
1 0 A17 A16
00 0 A10
A20 A19 A18
1 A21 A20 A19
01 0 A19 A18 A17
1 A20 A19 A18
1X 0 A18 A17 A16
1 A19 A18 A17
DSP56009 User's Manual
0 0 A7 A[6:3]
0 0 A14 A[13:10]
0 0 A15 A[14:11] A10
0 0 A13 A[12:9]
0 0 A14 A[13:10]
0 0 A12 A[11:8]
0 0 A13 A[12:9]
0 A8 A7 A[6:3]
0 A16 A15 A[14:11] A10
0 A17 A16 A[15:12] A11 A10
0 A15 A14 A[13:10]
0 A16 A15 A[14:11] A10
0 A14 A13 A[12:9]
0 A15 A14 A[13:10]
A9 A8 A7 A[6:3]
A16 A[15:12] A11 A10
A17 A[16:13] A12 A11 A10
A15 A[14:11] A10
A16 A[15:12] A11 A10
A14 A[13:10]
A15 A[14:11] A10
A9 A8 A7 A[6:3]
A17 A[16:13] A12 A11
A18 A[17:14] A13 A12 A11
A16 A[15:12] A11
A17 A[16:13] A12 A11
A15 A[14:11]
A16 A[15:12] A11
A2 A1 A0
A9 A8 C0
A9 A8
A8 C0 C1
A9 A8 C0
C0 C1 C2
A8 C0 C1
A2 A1 A0
A9 C0
A9
A9 C0 C1
A9 C0
C0 C1 C2
A9 C0 C1
A2 A1 A0
C0
C0 C1
C0
C0 C1 C2
C0 C1
A2 A1 A0
C0
C0 C1
C0
C0 C1 C2
C0 C1
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