Figure 4-9 Illustration Of The Data-Delay Structure - Motorola DSP56009 User Manual

External Memory Interface
Data-delay Structure
4.6 DATA-DELAY STRUCTURE
Delayed data structures, commonly used in audio DSP algorithms, can be
implemented by means of data-delay buffers in memory. A data-delay buffer is a
bank of memory in which data samples are stored in a sequential manner and where
a relationship exists between time delay and memory location. The longest delay for
a given data sequence corresponds to the length of the data-delay buffer (the size of
the memory bank). Data-delay buffers of any length, within the available memory
range, are supported by the EMI.
A memory buffer for delayed data is defined in terms of a base address and a
collection of offset values (the taps). Data-delay buffers are implemented in the EMI
by means of "windows" that move over all the memory address range. The base
address points to the latest stored (newest) data sample, and offset values are
subtracted from the base address to generate addresses that point to delayed data
samples. The amount of the delay is defined by the offset value. Normally, the base
address of each data-delay buffer is incremented every time a new data sample is
stored and this causes the window to move one position ahead in the range of
physical memory addresses. The data-delay structure is illustrated in Figure 4-9.
Points to Delayed
Data Sample.
Ascending
Address
Progression
Over The
Entire
Memory
Space.
Illustration of One data-delay Buffer
Moving Along the Memory Address Range
Region of valid delayed data

Figure 4-9 Illustration of the Data-Delay Structure

4-46
Base Address
Offset (Points to Latest Data Sample).
Value
Buffer 0
Pointer
(EBAR)
DSP56009 User's Manual
Illustration of Two Independent
Data-delay Buffers of Different Lengths
Buffer 1
Pointer
(EBAR)
AA0401
MOTOROLA