Figure 5-9 Acknowledgment On The I 2 C Bus - Motorola DSP56009 User Manual

Serial Host Interface
Characteristics Of The I
Start
Event
SCL From
Master Device
Data Output
by Transmitter
S
Data Output
by Receiver
By definition, a device that generates a signal is called a "transmitter," and the device
that receives the signal is called a "receiver." The device that controls the signal is
called the "master" and the devices that are controlled by the master are called
"slaves". A master receiver must signal an end-of-data to the slave transmitter by not
generating an acknowledge on the last byte that has been clocked out of the slave
device. In this case the transmitter must leave the data line high to enable the master
generation of the Stop event. Handshaking may also be accomplished by use of the
clock synchronizing mechanism. Slave devices can hold the SCL line low, after
receiving and acknowledging a byte, to force the master into a wait state until the
slave device is ready for the next byte transfer. The SHI supports this feature when
operating as a master device and will wait until the slave device releases the SCL line
before proceeding with the data transfer.
2
5.5.2 I C Data Transfer Formats
2
I C bus data transfers follow the following format: after the Start event, a slave device
address is sent. This address is 7 bits wide, the eighth bit is a data direction bit
(R/W); '0' indicates a transmission (write), and '1' indicates a request for data (read).
A data transfer is always terminated by a Stop event generated by the master device.
However, if the master device still wishes to communicate on the bus, it can generate
another Start event, and address another slave device without first generating a Stop
event (this feature is not supported by the SHI when operating as an I
device). This method is also used to provide indivisible data transfers. Various
combinations of read/write formats are illustrated in Figure 5-10 and Figure 5-11.
5-22
2
C Bus
1
Figure 5-9 Acknowledgment on the I
DSP56009 User's Manual
2
2
C Bus
Clock Pulse For
Acknowledgment
8 9
AA0424
2
C master
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