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Serial Audio Interface
Serial Audio Interface Programming Model
6.3
SERIAL AUDIO INTERFACE PROGRAMMING MODEL
The Serial Audio Interface registers that are available to the programmer are shown
in Figure 6-4 . The registers are described in the following paragraphs.
23
16
15
14
13
23
16
15
14
13
RRDF
RLDF
23
16
15
14
13
TRDE
TLDE
Reserved Bit(s)
The SAI interrupt vectors can be located in either of two different regions in memory.
The transmit interrupt vector locations are controlled by TXIL bit in the Transmit
Control Status (TCS) register. Similarly, the receive interrupt vector locations are
controlled by RXIL bit in the Receive Control Status (RCS) register. The interrupt
vector locations for the SAI are shown in Table 6-1 . The interrupts generated by the
SAI are prioritized as shown in Table 6-2 .
6-8
Baud Rate Control Register (BRC)
12
11
10
Receive Control/Status Register (RCS)
12
11
10
9
RXIL
RXIE
RDWT
RREL
Transmit Control/Status Register (TCS)
12
11
10
9
TXIL
TXIE
TDWE
TREL
23
23
23
23
23
Figure 6-4 SAI Registers
DSP56009 User's Manual
X: $FFE0
9
8
7
6
PSR
PM7
PM6
PM5
X: $FFE1
8
7
6
5
RCKP
RLRS
RDIR
RWL1
X: $FFE4
8
7
6
5
TCKP
TLRS
TDIR
TWL1
0
Receiver 0 Data Register
read-only
X: $FFE2
0
Receiver 1 Data Register
read-only
X: $FFE3
0
Transmitter 0 Data Register
write-only
X: $FFE5
0
Transmitter 1 Data Register
write-only
X: $FFE6
0
Transmitter 2 Data Register
write-only
X: $FFE7
5
4
3
2
PM4
PM3
PM2
PM1
4
3
2
1
RWL0
RMST
R1EN
4
3
2
1
TWL0
TMST
T2EN
T1EN
MOTOROLA
1
0
PM0
0
R0EN
0
T0EN
AA0430k
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