Hcsr Host Busy (Hbusy)—Bit 22 - Motorola DSP56009 User Manual

24-bit digital signal processor
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Serial Host Interface
Characteristics Of The SPI Bus
5.3.6.18
HCSR Host Busy (HBUSY)—Bit 22
2
The read-only status bit Host Busy (HBUSY) indicates that the I
C bus is busy (when
2
in the I
C mode) or that the SHI itself is busy (when in the SPI mode). When
2
operating in the I
C mode, HBUSY is set after the SHI detects a Start event and
remains set until a Stop event is detected. When operating in the Slave SPI mode,
HBUSY is set while SS is asserted. When operating in the Master SPI mode, HBUSY is
set if the HTX register is not empty or if the IOSR is not empty. HBUSY is cleared
otherwise. HBUSY is cleared by hardware reset, software reset, SHI individual reset,
and during the Stop state.
5.4
CHARACTERISTICS OF THE SPI BUS
The SPI bus consists of two serial data lines (MISO and MOSI), a clock line (SCK),
and a Slave Select line (SS).
5.4.1
Overview
During an SPI transfer, a byte is shifted out one data pin while a different byte is
simultaneously shifted in through a second data pin. It can be viewed as two 8-bit
shift registers connected together in a circular manner, where one shift register is
located on the master side and the other on the slave side. Thus the data bytes in the
master device and slave device are effectively exchanged. The MISO and MOSI data
pins are used for transmitting and receiving serial data. When the SPI is configured
as a master, MISO is the master data input line, and MOSI is the master data output
line. When the SPI is configured as a slave device, these pins reverse roles.
Clock control logic allows a selection of clock polarity and a choice of two
fundamentally different clocking protocols to accommodate most available
synchronous serial peripheral devices. When the SPI is configured as a master, the
control bits in the HCKR select the appropriate clock rate, as well as the desired clock
polarity and phase format (see Figure 5-6 on page 5-10).
The SS line allows individual selection of a slave SPI device; slave devices that are not
selected do not interfere with SPI bus activity (i.e., they keep their MISO output pin
in the high-impedance state). When the SHI is configured as an SPI master device,
the SS line should be held high. If the SS line is driven low when the SHI is in SPI
Master mode, a bus error will be generated (the HCSR HBER bit will be set).
MOTOROLA
DSP56009 User's Manual
5-19

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