Motorola DSP56009 User Manual page 46

Signal Descriptions
External Memory Interface (EMI)
Table 2-5 External Memory Interface (EMI) Signals (Continued)
Signal
Signal Name
MA15/MCS3 Output
MA16/MCS2/ Output
MCAS
MA17/MCS1/ Output
MRAS
MCS0 Output
MWR Output
MRD Output
MD0–MD7
directional
2-8
State
during
Type
Reset
Table 2-6
Table 2-6
Table 2-6
Table 2-6
Table 2-6
Table 2-6
Bi- Tri-stated
DSP56009 User's Manual
Signal Description
Memory Address Line 15 (MA15)/Memory
Chip Select 3 (MCS3)—This line functions as
the non-multiplexed address line 15 or as
memory chip select 3 for SRAM accesses.
Memory Address Line 16 (MA16)/Memory
Chip Select 2 (MCS2)/Memory Column
Address Strobe (MCAS)— This line functions
as the non-multiplexed address line 16 or as
memory chip select 2 for SRAM accesses. This
line also functions as the Memory Column
Address Strobe (MCAS) during DRAM
accesses.
Memory Address Line 17 (MA17)/Memory
Chip Select 1 (MCS1)/Memory Row Address
Strobe (MRAS)—This line functions as the
non-multiplexed address line 17 or as chip
select 1 for SRAM accesses. This line also
functions as the Memory Row Address Strobe
during DRAM accesses.
Memory Chip Select 0—This line functions as
memory chip select 0 for SRAM accesses.
Memory Write Strobe—This line is asserted
when writing to external memory.
Memory Read Strobe—This line is asserted
when reading external memory.
Data Bus—These signals provide the
bidirectional data bus for EMI accesses. They
are inputs during reads from external memory,
outputs during writes to external memory, and
tri-stated if no external access is taking place. If
the data bus width is defined as four bits wide,
only signals MD0–MD3 are active, while signals
MD4–MD7 remain tri-stated. While tri-stated,
MD0–MD7 are disconnected from the pins and
do not require external pull-ups.
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