Motorola DSP56009 User Manual page 9

5.3 SERIAL HOST INTERFACE PROGRAMMING MODEL . . . . 5-5
5.3.1 SHI Input/Output Shift Register (IOSR)—Host Side . . . . . 5-8
5.3.2 SHI Host Transmit Data Register (HTX)—DSP Side. . . . . 5-8
5.3.3 SHI Host Receive Data FIFO (HRX)—DSP Side . . . . . . . 5-9
5.3.4 SHI Slave Address Register (HSAR)—DSP Side . . . . . . . 5-9
5.3.4.1 HSAR Reserved Bits—Bits 17–0,19 . . . . . . . . . . . . . . . 5-9
5.3.4.2 HSAR I
(HA[6:3], HA1)—Bits 23–20,18 . . . . . . . . . . . . . . . . . . . 5-9
5.3.5 SHI Clock Control Register (HCKR)—DSP Side . . . . . . . . 5-9
5.3.5.1 Clock Phase and Polarity
(CPHA and CPOL)—Bits 1–0 . . . . . . . . . . . . . . . . . . . 5-10
5.3.5.2 HCKR Prescaler Rate Select (HRS)—Bit 2 . . . . . . . . 5-11
5.3.5.3 HCKR Divider Modulus Select
(HDM[5:0])—Bits 8–3 . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
5.3.5.4 HCKR Reserved Bits—Bits 23–14, 11–9 . . . . . . . . . . 5-12
5.3.5.5 HCKR Filter Mode (HFM[1:0]) — Bits 13–12 . . . . . . . 5-12
5.3.6 SHI Control/Status Register (HCSR)—DSP Side . . . . . . 5-13
5.3.6.1 HCSR Host Enable (HEN)—Bit 0 . . . . . . . . . . . . . . . . 5-13
5.3.6.2 HCSR I
5.3.6.3 HCSR Serial Host Interface Mode
(HM[1:0])—Bits 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
5.3.6.4 HCSR Reserved Bits—Bits 23, 18, 16, and 4. . . . . . . 5-14
5.3.6.5 HCSR FIFO-Enable Control (HFIFO)—Bit 5. . . . . . . . 5-14
5.3.6.6 HCSR Master Mode (HMST)—Bit 6 . . . . . . . . . . . . . . 5-14
5.3.6.7 HCSR Host-Request Enable
(HRQE[1:0])—Bits 8–7 . . . . . . . . . . . . . . . . . . . . . . . . 5-15
5.3.6.8 HCSR Idle (HIDLE)—Bit 9 . . . . . . . . . . . . . . . . . . . . . 5-15
5.3.6.9 HCSR Bus-Error Interrupt Enable (HBIE)—Bit 10 . . . 5-16
5.3.6.10 HCSR Transmit-Interrupt Enable (HTIE)—Bit 11 . . . . 5-16
5.3.6.11 HCSR Receive Interrupt Enable
(HRIE[1:0])—Bits 13–12 . . . . . . . . . . . . . . . . . . . . . . . 5-16
5.3.6.12 HCSR Host Transmit Underrun Error
(HTUE)—Bit 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
5.3.6.13 HCSR Host Transmit Data Empty (HTDE)—Bit 15. . . 5-17
5.3.6.14 Host Receive FIFO Not Empty (HRNE)—Bit 17 . . . . . 5-18
5.3.6.15 Host Receive FIFO Full (HRFF)—Bit 19 . . . . . . . . . . . 5-18
MOTOROLA
2
C Slave Address
2
C/SPI Selection (HI2C)—Bit 1. . . . . . . . . . . . 5-13
DSP56009 User's Manual vii