Motorola DSP56009 User Manual page 51

Signal Descriptions
Interrupt and Mode Control
Table 2-7 Interrupt and Mode Control Signals (Continued)
Signal Signal State during
Signal Description
Name Type Reset
RESET input active RESET—This input causes a direct hardware reset of
the processor. When RESET is asserted, the DSP is
initialized and placed in the Reset state. A
Schmitt-trigger input is used for noise immunity. When
the reset signal is deasserted, the initial DSP operating
mode is latched from the MODA, MODB, and MODC
signals. The DSP also samples the PINIT signal and
writes its status into the PEN bit of the PLL Control
Register. When the DSP comes out of the Reset state,
deassertion occurs at a voltage level and is not
directly related to the rise time of the RESET signal.
However, the probability that noise on RESET will
generate multiple resets increases with increasing
rise time of the RESET signal.
For proper hardware reset to occur, the clock must be
active, since a number of clock ticks are required for
proper propagation of the hardware reset state.
MOTOROLA DSP56009 User's Manual 2-13