Figure 4-13 Fast Read Or Write Dram Access Timing-1; Fast Timing Mode - Motorola DSP56009 User Manual

External Memory Interface
EMI Timing
4.8.1.1

Fast Timing Mode

Figure 4-13 shows the Absolute Addressing mode timing for an 8-bit word/8-bit bus
memory access or physical memory access. The numbers in the table are
memory-access clock cycles and correspond to clock cycles of the timing figure
directly below. Data accesses are left-justified such that the 8-bit word is read from
and written into the upper-most byte of the 24-bit word (bits 23–16).
8-bit word/8-bit bus—Relative Addressing, or each physical access in
Set up row address
R/W Bits 23–16
Finish last R/W cycle
Start new memory
cycle
Figure 4-13 Fast Read or Write DRAM Access Timing—1
4-52
the Absolute Addressing modes
1 2
CLK
Row
Address
Address
MRAS
MCAS
Read
MRD
MWR
Data In
Write
MWR
MRD
Data Out
DSP56009 User's Manual
3
4 5 6
7
Column
Address
Valid
Data
Valid
Data
8
1 2
Row
Address
AA0403
MOTOROLA