Sram Relative Addressing - Motorola DSP56009 User Manual

EBARx and EOR are written to the ALU. The contents of EBARx or EOR should not
be changed during word transfers. The SRAM Absolute Addressing mode is useful
when accessing external peripherals or memories that contain program segments,
cases where it is important to have a one-to-one correspondence between the word
address and the external physical location. This mode can be used concurrently with
either the SRAM Relative Addressing or the DRAM Relative Addressing; that is, it is
possible to access static memory devices or peripherals using the Absolute
Addressing mode while having data-delay buffers implemented in either SRAM or
DRAM memories. Note that it is assumed that the device select for the devices being
addressed with the Absolute Addressing mode is provided by circuits that are
external to the EMI, such as a GPIO signal. While in the SRAM Absolute Addressing
mode, refresh of DRAMs connected to the EMI will continue if the refresh is enabled
in the ERCR.
4.3.2

SRAM Relative Addressing

The SRAM Relative Addressing modes (EAM[3:0] = 0001, 0010, 0011) are used to
implement data-delay buffers in SRAM. In this addressing mode, the physical
addresses required are formed by taking some LSBs of the calculated word address
and appending from 0 to 3 extension bits to the right of the word address (forming
the LSBs of the physical address). The extension bits are then used to generate the
number of physical addresses required.
• When EAM[3:0]= 0001, it is possible to connect directly a single 4-bit or 8-bit
wide SRAM device of up to 256 K addresses, since only MCS0 is active for any
access.
• When EAM[3:0] = 0010, it is possible to connect directly up to two 4-bit or 8-bit
wide SRAM devices with up to 128 K addresses each, since MCS0 and MCS1
are active.
• When EAM[3:0] = 0011, it is possible to connect directly up to four 4-bit or
8-bit wide SRAM devices with up to 32 K addresses each, since MCS0, MCS1,
MCS2, and MCS3 are active.
Note: In this addressing mode, if the word length is 20 bits or 24 bits (or 16 bits using
24-bit addressing), it is possible to connect only three SRAMs (and save
memory), since MCS0 will not be activated at all.
Table 4-13 summarizes the address generation for the SRAM Addressing modes.
MOTOROLA DSP56009 User's Manual
External Memory Interface
EMI Address Generation
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