Figure 4-16 Fast Read Or Write Dram Access Timing-4 - Motorola DSP56009 User Manual

Figure 4-16 shows the timing using Relative Addressing mode for a 20-bit
word/8-bit bus memory access, 24-bit word/8-bit bus memory access, or 12-bit
word/4-bit bus memory access. The numbers in the table are memory-access clock
cycles and correspond to clock cycles of the timing figure directly below. Data
accesses are left-justified such that the 20-bit, 24-bit, or 12-bit word is read from and
written into the upper-most 20, 24, or 12 bits of the 24-bit word. Data is transferred
one byte at a time for 16- and 20-bit words or four bits at time for 12-bit words.
20-bit or 24-bit word/8-bit bus, or 12-bit word/4-bit bus—Relative Addressing
Set up row address
R/W Bits 23–16
R/W Bits 15–8
R/W Bits 7–4/0
Finish last R/W cycle
New memory cycle
CLK
Address
MRAS
MCAS
Read
MRD
MWR
Data In
Write
MWR
MRD
Data Out
Figure 4-16 Fast Read or Write DRAM Access Timing—4
MOTOROLA
1 2 3
4 5
7 8
Row Column
Address Address
Valid
Data
DSP56009 User's Manual
External Memory Interface
6
9
10 11 12
Last Column
Address
Valid Valid
Data Data
Valid
Data
EMI Timing
13 14
1 2
Row
Address
AA0406
4-55