Table of Contents
Advertisement
Memory, Operating Modes, and Interrupts
DSP56009 Data And Program Memory Maps
3.3.1
Dynamic Switching of Memory Configurations
The internal memory configuration is altered by re-mapping RAM modules from X
and Y data memories into program memory space and vise-versa. Data contents of
the switched RAM modules are preserved.
The memory can be dynamically switched from one configuration to another by
changing PEA and PEB bits in OMR. The address ranges that are directly affected by
the switch operation are P:$0200...$0AFF, X:$0C00...$11FF and Y:$0E00...$10FF (see
Figure 3-1 on page 3-6, Figure 3-2 on page 3-6, Figure 3-3 on page 3-7, and
Figure 3-4). The memory switch can be accomplished provided that the affected
address ranges are not being accessed during the instruction cycle in which the
switch operation takes place. Specifically, these two conditions must be observed for
troublefree dynamic switching:
• No accesses to or from X:$0C00...$11FF or Y:$0E00...$10FF are allowed during
the switch cycle.
• No accesses (including instruction fetches) to/from P:$0200...$0AFF are
allowed during the switch cycle.
Note: The switch actually occurs 3 instruction cycles after the instruction that
modifies PEA/PEB bits.
Any sequence that complies with the switch conditions is valid. For example, if the
program flow executes in the address range that is not affected by the switch (other
than P:$0200...$0AFF), the switch conditions can be met very easily. In this case a
switch can be accomplished by just changing PEA/PEB bits in OMR in the regular
program flow, assuming no accesses to X:$0C00...$11FF or Y:$0E00...$10FF occur up
to 3 instructions after the instruction that changes the OMR bits.
A more intricate case is that in which a switch memory operation takes place while
the program flow is being executed (or should proceed) in the affected program
address range (P:$0200...$0AFF). In this case, a particular switch sequence should be
performed. Interrupts must be disabled before executing the switch sequence, since
an interrupt could cause the DSP to fetch instructions out of sequence. The interrupts
must be disabled at least 4 instruction cycles before switching, due to pipeline latency
of the interrupt processing.
Special attention should be given when running a memory switch routine using the
OnCE port. Running the switch routine in Trace mode, for example, can cause the
switch to complete after the PEA/PEB bit changes while the DSP is in Debug mode.
As a result, subsequent instructions might be fetched according to the new memory
configuration (after the switch), and thus might execute improperly. A general
3-8
DSP56009 User's Manual
MOTOROLA
Advertisement
Table of Contents
