Table of Contents
Advertisement
R
Phase Lock Loop (PLL) 1-12
PLL (Phase Lock Loop)
Multiplication Factor (MF) bits 3-18
PLL (Phase-Locked Loop)
Control Register (PCTL) B-17
PLL Signals 2-6
PLL Filter Off-Chip Capacitor (PCAP) 2-7
PM0-PM7 (BRC Prescale Modulus Select) 6-10
Port A (External Memory Interface) 1-18
Program Control Unit 1-12
Program Memory 1-13
Program Overlay C-5
Program RAM Enable A (PEA) bit 3-11
Program RAM Enable B (PEB) bit 3-12
Programming
3 Tap FIR Filter C-10
Early Reflection Filter C-6
Overlay C-5
SAI Considerations 6-24
Single Delay Line C-5
Transmitter Clock Polarity (TCKP) 6-20
Transmitter Data Shift Direction (TDIR) 6-19
Transmitter Data Word Expansion
(TDWE) 6-21
Transmitter Left Right Selection (TLRS) 6-19
Two Channel Comb Filter C-7
Programming Model
EMI 4-5
GPIO 7-3
SAI 6-8
SHI—DSP Side 5-6
SHI—Host Side 5-5
Programming Sheets — See Appendix B
PSR (BRC Prescaler Range) 6-10
R
R0EN (RCS Receiver 0 Enable) 6-10
R1EN (RCS Receiver 1 Enable) 6-11
RCKP (RCS Receiver Clock Polarity) 6-13
RCS (Receiver Control/Status Register) 6-10
RDIR (RCS Receiver Data Shift Direction) 6-12
RDWT (RCS Receiver Data Word
Truncation) 6-14
RLDF (RCS Receiver Left Data Full) 6-16
RLRS (RCS Receiver Left Right Selection) 6-12
RMST (RCS Receiver Master) 6-11
RRDF (RCS Receiver Right Data Full) 6-16
Index-4
RWL0-RWL1 (RCS Receiver Word Length
RX0 and RX1 (Receive Data Registers) 6-17
RXIE (RCS Receiver Interrupt Enable) 6-15
RXIL (RCS Receiver Interrupt Location) 6-15
S
SAI 6-3
DSP56009 User's Manual
Control) 6-11
Baud Rate Control Register (BRC) 6-9
Baud Rate Generator 6-4
BRC
Prescale Modulus Select 6-10
Prescaler Range 6-10
Reserved Bits 6-10
Initiating A Transmit Session 6-24
Internal Architecture 6-4
Internal Interrupt Priorities 6-9
Operation During Stop 6-24
Operation Under Irregular Conditions 6-25
Programming Considerations 6-24
Programming Model 6-8
RCS
Receiver 0 Enable 6-10
Receiver 1 Enable 6-11
Receiver Clock Polarity 6-13
Receiver Data Shift Direction 6-12
Receiver Data Word Truncation 6-14
Receiver Interrupt Enable 6-15
Receiver Interrupt Location 6-15
Receiver Left Data Full 6-16
Receiver Left Right Selection 6-12
Receiver Master 6-11
Receiver Relative Timing 6-13
Receiver Right Data Full 6-16
Receiver Word Length Control 6-11
Receive Data Registers 6-17
Receive Section 6-5
Receive Section Block Diagram 6-5
Receiver Clock Polarity (RCKP)
Programming 6-13
Receiver Clock Polarity Programming 6-13
Receiver Control/Status Register 6-10
Receiver Data Shift Direction (RDIR)
Programming 6-12
Receiver Data Word Truncation (RDWT)
Programming 6-14
Receiver Left Right Selection (RLRS)
Programming 6-12
MOTOROLA
Advertisement
Table of Contents
