Figure 4-19 Slow Read Or Write Dram Access Timing-1; Slow Timing Mode - Motorola DSP56009 User Manual

External Memory Interface
EMI Timing
4.8.1.2

Slow Timing Mode

Figure 4-19 shows the Absolute Addressing mode timing for an 8-bit word/8-bit bus
memory access or physical memory access. The numbers in the table are
memory-access clock cycles and correspond to clock cycles of the timing figure
directly below. Data accesses are left-justified such that the 8-bit word is read from
and written into the upper-most byte of the 24-bit word (bits 23–16).
8-bit word/8-bit bus—Relative Addressing, or each physical access in the
Set up row address
R/W Bits 23–16
Finish last R/W cycle
New memory cycle
Figure 4-19 Slow Read or Write DRAM Access Timing—1
4-58
Absolute Addressing modes
1 2 3
CLK
Row
Address
Address
MRAS
MCAS
Read
MRD
MWR
Data In
Write
MWR
MRD
Data Out
DSP56009 User's Manual
4
5 6 7 8
9 10 11 12
Column
Address
Valid
Data
Valid
Data
1 2
Row
Address
AA0409
MOTOROLA