Figure 4-20 Slow Read Or Write Dram Access Timing-2 - Motorola DSP56009 User Manual

Figure 4-20 shows the timing using Relative Addressing mode for a 16-bit
word/8-bit bus memory access or 8-bit word/4-bit bus memory access. The numbers
in the table are memory access clock cycles and correspond to clock cycles of the
timing figure directly below. Data accesses are left justified such that the 16-bit word
is read from and written into the upper-most two bytes of the 24-bit word (bits 23–8).
Data is transferred one byte at a time for 16-bit words or four bits at time for 8-bit
words.
16-bit word/8-bit bus, or 8 bit word/4-bit bus—Relative Addressing
Set up row address
R/W bits 23–16; 23–20
R/W bits 15–8; 19–16
Finish last R/W cycle
New memory cycle
CLK
Address
MRAS
MCAS
Read
MRD
MWR
Data In
Write
MWR
MRD
Data Out
Figure 4-20 Slow Read or Write DRAM Access Timing—2
MOTOROLA
1 2 3 4
5 6
Row Column
Address Address
Valid
Data
DSP56009 User's Manual
External Memory Interface
7 8
9 10 11 12
Last Column
Address
Valid Valid
Data Data
Valid
Data
EMI Timing
13 14 15 16
1 2
Row
Address
AA0410
4-59