Figure 4-22 Slow Read Or Write Dram Access Timing-4 - Motorola DSP56009 User Manual

Figure 4-22 shows the timing using Relative Addressing mode for an 20-bit
word/8-bit bus memory access, 24-bit word/8-bit bus memory access, or 12-bit
word/4-bit bus memory access. The numbers in the table are memory access clock
cycles and correspond to clock cycles of the timing figure directly below. Data
accesses are left justified such that the 20-bit, 24-bit, or 12-bit word is read from and
written into the upper-most 20-bits, 24-bits, or 12-bits of the 24-bit word. Data is
transferred one byte at a time for 16-bit and 12-bit words or four bits at time for 12-bit
words.
20-bit or 24-bit word/8-bit bus, or 12-bit word/4-bit bus—Relative Addressing
Set up row address
R/W Bits 23–16; 23–20
R/W Bits 15–8; 19–16
R/W Bits 7–4/0; 15–12
Finish last R/W cycle
New memory cycle
CLK
Address
MRAS
MCAS
Read
MRD
MWR
Data In
Write
MWR
MRD
Data Out
Figure 4-22 Slow Read or Write DRAM Access Timing—4
MOTOROLA
1 2 3 4
5 6
9 10 11 12
Row Column
Address Address
Valid
Data
DSP56009 User's Manual
External Memory Interface
7 8
13 14 15 16
Last Column
Address
Valid Valid
Data Data
Valid
Data
EMI Timing
17 18 19 20
1 2
Row
Address
AA0412
4-61