Table of Contents
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Replacing DRAMs with SRAMs for Large Arrays. . . . . . . . . . . . 4-50
Fast Read or Write DRAM Access Timing-1 . . . . . . . . . . . . . . 4-52
Fast Read or Write DRAM Access Timing-2 . . . . . . . . . . . . . . 4-53
Fast Read or Write DRAM Access Timing-3 . . . . . . . . . . . . . . 4-54
Fast Read or Write DRAM Access Timing-4 . . . . . . . . . . . . . . 4-55
Fast Read or Write DRAM Access Timing-5 . . . . . . . . . . . . . . 4-56
Fast Read or Write DRAM Access Timing-6 . . . . . . . . . . . . . . 4-57
Slow Read or Write DRAM Access Timing-1. . . . . . . . . . . . . . 4-58
Slow Read or Write DRAM Access Timing-2. . . . . . . . . . . . . . 4-59
Slow Read or Write DRAM Access Timing-3. . . . . . . . . . . . . . 4-60
Slow Read or Write DRAM Access Timing-4. . . . . . . . . . . . . . 4-61
Slow Read or Write DRAM Access Timing-5. . . . . . . . . . . . . . 4-62
Slow Read or Write DRAM Access Timing-6. . . . . . . . . . . . . . 4-63
SRAM Read/Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-64
Serial Host Interface Block Diagram . . . . . . . . . . . . . . . . . . . . . . 5-4
SHI Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
SHI Programming Model-Host Side. . . . . . . . . . . . . . . . . . . . . . 5-5
Figure 5-4
SHI Programming Model-DSP Side. . . . . . . . . . . . . . . . . . . . . . 5-6
SHI I/O Shift Register (IOSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
SPI Data-To-Clock Timing Diagram. . . . . . . . . . . . . . . . . . . . . . 5-10
2
Figure 5-7
I
C Bit Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20
2
C Start and Stop Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21
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DSP56009 User's Manual
MOTOROLA
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