Ac Timings - Motorola Digital DNA MSC8101 Technical Data Manual

2.7 AC Timings

The following sections include illustrations and tables of clock diagrams, signals, and parallel I/O outputs
and inputs. AC timings are based on a 50 pF load, except where noted otherwise, and 50 Ω transmission
line.
2.7.1 Clocking and Timing Characteristics
Phase Jitter between BCLK and DLLIN
CLKIN frequency
CLKIN slope
DLLIN slope
CLKOUT frequency jitter
Delay between CLKOUT and DLLIN
Notes:
Input Clock
SPLL MF Clock
Bus
Output
Serial Communications Controller
Communications Processor
Module
SC140 Core
Baud Rate Generator
•
•
•
•
Table 2-9. System Clock Parameters
Characteristic
1,2
1. Low CLKIN frequency causes poor PLL performance. Choose a CLKIN frequency high enough to keep
the frequency after the predivider (SPLLMFCLK) higher than 18 MHz.
CLKIN should have a 50% ± 5% duty cycle.
2.
Clock
SPLLMFCLK
For BRG DF = 4
For BRG DF = 16 (default)
For BRG DF = 64
For BRG DF = 256
Minimum
—
18
—
—
—
—
Table 2-10. Clock Ranges
Maximum Rated Core Frequency
Symbol All Max. Values for SC140 Clock Rating of:
Min
CLKIN 18 MHz
18 MHz
BCLK 18 MHz
CLKOUT 43.2 MHz
SCLK 18 MHz
CPMCLK 36 MHz
DSPCLK 72 MHz
BRGCLK
36 MHz
9 MHz 15.63 MHz
2.25 MHz
562.5 KHz 976.6 KHz
AC Timings
Maximum
0.5
75
5
2
(0.01 × CLKOUT) + CLKIN jitter
5
250 MHz 275 MHz
62.5 68.75 MHz
20.83 22.9 MHz
62.5 MHz 68.75 MHz
62.5 MHz 68.75 MHz
62.5 MHz 68.75 MHz
125 MHz 137.5 MHz
250 MHz 275 MHz
62.5 MHz 68.75 MHz
17.19 MHz
3.91 MHz 4.30 MHz
1.07 MHz
Unit
ns
MHz
ns
ns
ns
ns
300 MHz
75 MHz
25 MHz
75 MHz
75 MHz
75 MHz
150 MHz
300 MHz
75 MHz
18.75 MHz
4.69 MHz
1.17 MHz
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