Control Registers - Epson S1C17F13 Technical Manual

19 R/F CONVERTER (RFC)
19.6

Control Registers

RFC Ch.n Clock Control Register
Register name Bit
RFCnCLK 15–9 –
8
7–6 –
5–4 CLKDIV[1:0]
3–2 –
1–0 CLKSRC[1:0]
Bits 15–9 Reserved
Bit 8 DBRun
This bit sets whether the RFC operating clock is supplied in DEBUG mode or not.
1 (R/W): Clock supplied in DEBUG mode
0 (R/W): No clock supplied in DEBUG mode
Bits 7–6 Reserved
Bits 5–4 ClKDiV[1:0]
These bits select the division ratio of the RFC operating clock.
Bits 3–2 Reserved
Bits 1–0 ClKSRC[1:0]
These bits select the clock source of the RFC.
RFCnCLK.
CLKDIV[1:0] bits
0x3
0x2
0x1
0x0
(Note) The oscillation circuits/external input that are not supported in this IC cannot be
selected as the clock source.
Note: The RFCnCLK register settings can be altered only when the RFCnCTL.MODEN bit = 0.
RFC Ch.n Control Register
Register name Bit
RFCnCTL 15–9 –
8
7
6
5–4 SMODE[1:0]
3–1 –
0
Bits 15–9 Reserved
Bit 8 RFClKMD
This bit sets the RFCLKOn pin to output the divided-by-two oscillation clock.
1 (R/W): Divided-by-two clock output
0 (R/W): Oscillation clock output
For more information, refer to "CR Oscillation Frequency Monitoring Function."
19-8
Bit name Initial
0x00
DBRUN 1
0x0
0x0
0x0
0x0
Table 19. 6.1 Clock Source and Division Ratio Settings
0x0
OSC3B
Bit name Initial
0x00
RFCLKMD 0
CONEN 0
EVTEN 0
0x0
0x0
MODEN 0
Seiko epson Corporation
Reset R/W
– R –
H0 R/W
– R
H0 R/W
– R
H0 R/W
RFCnCLK.CLKSRC[1:0] bits
0x1 0x2
OSC1 OSC3A
1/8
1/4
1/2
1/1
Reset R/W
– R –
H0 R/W
H0 R/W
H0 R/W
H0 R/W
– R
H0 R/W
Remarks
0x3
EXOSC
1/1
Remarks
S1C17F13 TeChniCal Manual
(Rev. 1.0)