Epson S1C17F13 Technical Manual page 30

5. Write a value other than 0x0096 to the MSCPROT.PROT[15:0] bits. (Set system protection)
6. Write 1 to the CLGOSC.OSC3AEN bit.
7. OSC3ACLK can be used if the CLGINTF.OSC3ASTAIF bit = 1 after an interrupt occurs.
The setting values of the CLGOSC3A.INVN[1:0] and CLGOSC3A.OSC3AWT[1:0] bits should be determined
after performing evaluation using the populated circuit board.
Oscillation start procedure for the OSC1B oscillator circuit
Follow the procedure shown below to start oscillation of the OSC1B oscillator circuit.
1. Write 1 to the CLGINTF.OSC1STAIF bit.
2. Write 1 to the CLGINTE.OSC1STAIE bit.
3. Write 0x0096 to the MSCPROT.PROT[15:0] bits. (Remove system protection)
4. Configure the following CLGOSC1 register bits:
- CLGOSC1.OSC1WT[1:0] bits
- Set the CLGOSC1.OSC1SEL bit to 1.
5. Write a value other than 0x0096 to the MSCPROT.PROT[15:0] bits. (Set system protection)
6. Write 1 to the CLGOSC.OSC1EN bit.
7. OSC1CLK can be used if the CLGINTF.OSC1STAIF bit = 1 after an interrupt occurs.
Oscillation start procedure for the OSC1A oscillator circuit
Follow the procedure shown below to start oscillation of the OSC1A oscillator circuit.
1. Write 1 to the CLGINTF.OSC1STAIF bit.
2. Write 1 to the CLGINTE.OSC1STAIE bit.
3. Write 0x0096 to the MSCPROT.PROT[15:0] bits. (Remove system protection)
4. Configure the following CLGOSC1 register bits according to the resonator used:
- CLGOSC1.OSC1WT[1:0] bits
- Set the CLGOSC1.OSC1SEL bit to 0.
5. Write a value other than 0x0096 to the MSCPROT.PROT[15:0] bits. (Set system protection)
6. Write 1 to the CLGOSC.OSC1EN bit.
7. OSC1CLK can be used if the CLGINTF.OSC1STAIF bit = 1 after an interrupt occurs.
The setting value of the CLGOSC1.OSC1WT[1:0] bits should be determined after performing evaluation using
the populated circuit board.
System clock switching
The CPU boots using OSC3BCLK as SYSCLK. After booting, the clock source of SYSCLK can be switched
according to the processing speed required. The SYSCLK frequency can also be set by selecting the clock
source division ratio, this makes it possible to run the CPU at the most suitable performance for the process to
be executed. The CLGSCLK.CLKSRC[1:0] and CLGSCLK.CLKDIV[1:0] bits are used for this control. The
CLGSCLK register bits are protected against writings by the system protect function, therefore, the system pro-
tection must be removed by writing 0x0096 to the MSCPROT.PROT[15:0] bits before the register setting can
be altered. For the transition between the operating modes including the system clock switching, refer to "Oper-
ating Mode."
Clock control in SLEEP mode
The CPU enters SLEEP mode when it executes the slp instruction. Whether the clock sources being operated
are stopped or not at this point can be selected in each source individually. This allows the CPU to fast switch
between SLEEP mode and RUN mode, and the peripheral circuits to continue operating without disabling the
clock in SLEEP mode. The CLGOSC.OSC3BSLPC, CLGOSC.OSC1SLPC, CLGOSC.OSC3ASLPC, and
CLGOSC.EXOSCSLPC bits are used for this control. Figure 2.3.4.2 shows a control example.
S1C17F13 TeChniCal Manual
(Rev. 1.0)
(Start oscillation)
(Clear interrupt flag)
(Enable interrupt)
(Set oscillation stabilization waiting time)
(Select OSC1B)
(Start oscillation)
(Clear interrupt flag)
(Enable interrupt)
(Set oscillation stabilization waiting time)
(Select OSC1A)
(Start oscillation)
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2 POWER SUPPLY, RESET, AND CLOCKS
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