Regulated Clock External Monitor; Control Register; Theoretical Regulation Control Register - Epson S1C17F13 Technical Manual

15.3.2

Regulated Clock External Monitor

Either the 256 Hz (F256) or 1 Hz (F1) corrected clock can be output from the REGMON pin for monitoring. The
control procedure is shown below.
Monitoring 256 Hz clock (F256)
1. Activate at least one peripheral circuit that uses F256 (the operating clock must be configured to F256).
2. Set the TRCTL.REGFREQ bit to 0.
3. Set the TRCTL.REGMONEN bit to 1.
Monitoring 1 Hz clock (F1)
1. Activate the real-time clock.
2. Set the TRCTL.REGFREQ bit to 1.
3. Set the TRCTL.REGMONEN bit to 1.
The clock is output from the REGMON pin by setting the TRCTL.REGMONEN bit to 1. Setting the TRCTL.REG-
MONEN bit to 0 stops the clock output and the REGMON pin goes low (V
15.4

Control Register

Theoretical Regulation Control Register

Register name Bit
TRCTL 15–10 –
9
8
7
6
5–0 TRIM[5:0]
Bits 15–10 Reserved
Bit 9 ReGFReQ
This bit selects the frequency of the regulated clock to be output from the REGMON pin for monitor-
ing.
1 (R/W): 1 Hz (F1)
0 (R/W): 256 Hz (F256)
Bit 8 ReGMOnen
This bit controls the regulated clock monitor output.
1 (R/W): Enable
0 (R/W): Disable
Note: Before the monitor output can be started, a peripheral circuit that uses the regulated clock
must be activated (see "Regulated Clock External Monitor").
Bit 7 ReGTRiG
This bit executes theoretical regulation.
1 (W): Trigger (Theoretical regulation is executed only once.)
0 (W): Ineffective
0 (R): Always 0 when being read
Note: A maximum 16.6 ms of delay occurs before theoretical regulation actually starts after writing
to the TRCTL.REGTRIG bit. Writing 1 to the TRCTL.REGTRIG bit in this period is ineffective,
so to write 1 to the TRCTL.REGTRIG bit successively, an interval at least 16.6 ms is neces-
sary between writings.
S1C17F13 TeChniCal Manual
(Rev. 1.0)
Bit name Initial
0x00
REGFREQ 0
REGMONEN 0
REGTRIG 0
– 0
0x00
Seiko epson Corporation
15 THEORETICAL REGULATION (TR)
(Select 256 Hz as the output frequency)
(Start clock monitor output)
(Select 1 Hz as the output frequency)
(Start clock monitor output)
) level.
SS
Reset R/W
– R –
H0 R/W
H0 R/W
H0 W Always read as 0.
– R –
H0 R/W
Remarks
15-3