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4 MEMORY AND BUS
note: When data is transferred to a memory in 32-bit access, the eight high-order bits are written to
the memory as 0x00 since the bit width of the S1C17 core general-purpose registers is 24 bits.
Conversely when sending from a memory to a register, the eight high-order bits are ignored.
The CPU performs 32-bit access for stack operations in an interrupt handling. In this case, the
CPU read/write 32-bit data that consists of the PSR value as the eight high-order bits and the
return address as the 24 low-order bits. For more information, refer to the "S1C17 Family S1C17
Core Manual."
The CPU adopts Harvard architecture that allows simultaneous processing of an instruction fetch and a data ac-
cess. However, they are not performed simultaneously under one of the conditions listed below. This prolongs the
instruction fetch cycle for the number of data area bus cycles.
• When the CPU executes an instruction stored in the Flash area and accesses data in the Flash area
• When the CPU executes an instruction stored in the internal RAM area and accesses data in the internal RAM
area
4.3
Flash Memory
The Flash memory is used to store application programs and data. Address 0x8000 in the Flash area is defined as
the vector table base address by default, therefore a vector table must be located beginning from this address. For
more information on the vector table, refer to "Vector Table" in the "Interrupt Controller" chapter.
4.3.1
Flash Bus Access Cycle Setting
There is a limit of frequency to access the Flash memory with no wait cycle, therefore, the number of bus access
cycles for reading must be changed according to the system clock frequency. The number of bus access cycles for
reading can be configured using the FLASHCWAIT.RDWAIT[1:0] bits. Select a setting for higher frequency than
the system clock.
4.3.2
Flash Programming
The Flash memory supports on-board programming, so it can be programmed with the ROM data by using the de-
bugger through an ICDmini. Figure 4.3.2.1 shows a connection diagram for on-board programming.
For detailed information on ROM data programming method, refer to the "(S1C17 Family C Compiler Package)
S5U1C17001C Manual." The IC can also be shipped after being programmed in the factory with the ROM data
developed. Should you desire to ship the IC with ROM data programmed from the factory, please contact our cus-
tomer support.
4-2
Table 4.
2.1 Number of Bus Access Cycles
Device size
Access size
8 bits
16 bits
32 bits
16 bits
16 bits
32 bits
32 bits
16 bits
32 bits
DCLK
V
DD
S1C17
R
DSIO
DST2
Figure 4.
3.2.1 External Connection
Seiko epson Corporation
Number of bus access
cycles
8 bits
1
2
4
8 bits
1
1
2
8 bits
1
1
1
DCLK
ICDmini
(S5U1C17001H)
DBG
DSIO
DST2
S1C17F13 TeChniCal Manual
(Rev. 1.0)
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