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15
Theoretical Regulation (TR)
15.1
Overview
TR is a theoretical regulation function that theoretically corrects time clock errors due to deviation in oscillation
frequencies. The main features of TR are outlined below.
• Adjusts the OSC1A clock (32.768 kHz Typ.).
(Note that other oscillation clocks cannot be adjusted.)
• Adjustable range: -31/32,768 to +32/32,768 seconds in a correction operation
• Allows software to execute theoretical regulation at any time.
Figure 15.1.1 shows the configuration of TR.
Peripheral circuits that can use the regulated clock (F256) in this IC
• Real-time clock
• Clock timer
• 16-bit PWM timer
TR
REGTRIG
TRIM[5:0]
OSC1A
oscillator
(32.768 kHz)
Clock generator
15.2
Output Pin
Table 15.2.1 shows the TR output pin.
Pin name
REGMON
If the port is shared with the REGMON pin and other functions, the REGMON function must be assigned to the
port before starting the monitor output. For more information, refer to the "I/O Ports" chapter.
15.3
Operations
15.3.1
Executing Theoretical Regulation
Follow the sequences shown below to execute theoretical regulation.
1. Set the correction value to the TRCTL.TRIM[5:0] bits.
2. Generate interrupts in the theoretical regulation execution cycles using a timer to perform theoretical regulation
periodically.
3. Write 1 to the TRCTL.REGTRIG bit (using the interrupt handler in Step 2). (Execute theoretical regulation)
S1C17F13 TeChniCal Manual
(Rev. 1.0)
Theoretical
F256 (256 Hz)
regulation
control circuit
F1 (1 Hz)
OSC1A
F256
divider
(256 Hz)
RTC reset
Figure 15.
1.1 TR Configuration
Table 15.
2.1 TR Output Pin
I/O*
Initial status*
O
O (L)
Seiko epson Corporation
15 THEORETICAL REGULATION (TR)
REGFREQ
REGMONEN
To peripheral circuits
Function
Theoretical regulation clock monitor output
* Indicates the status when the pin is configured for TR.
REGMON
15-1
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