Table of Contents
Advertisement
17 Parallel Interface (PIO)
PiO Control Register
Register name
Bit
PIOCTL
15–9 –
8
7–2 –
1
0
Bits 15–9 Reserved
Bit 8
RaCC
This bit starts a data read cycle.
1 (W):
Data read trigger
0 (W):
Ineffective
0 (R):
Always 0 when being read
Bits 7–2
Reserved
Bit 1
SFTRST
This bit issues software reset to PIO.
1 (W):
Issue software reset
0 (W):
Ineffective
0 (R):
Always 0 when being read
Setting this bit resets the PIO access control circuit. If 1 is written while a bus cycle is being executed,
the bus cycle is terminated at that point.
Bit 0
MODen
This bit enables the PIO operations.
1 (R/W): Enable PIO operations (The operating clock is supplied.)
0 (R/W): Disable PIO operations (The operating clock is stopped.)
Note: If the PIOCTL.MODEN bit is altered from 1 to 0 while a bus cycle is being executed, the
input/output data cannot be guaranteed. When setting the PIOCTL.MODEN bit to 1 again
after that, be sure to write 1 to the PIOCTL.SFTRST bit as well.
PiO address/Write Data Register
Register name
Bit
PIOWRDAT
15–8 PADDR[7:0]
7–0 PWDATA[7:0]
Bits 15–8 PaDDR[7:0]
These bits are used to set an address to be accessed.
Bits 7–0
PWDaTa[7:0]
These bits are used to set output data.
Writing to the PIOWRDAT register starts a data write cycle.
Notes: • If writing 1 to the PIOCTL.RACC bit and writing to the PIOWRDAT register are performed at a
time (read and write triggers are issued at the same time), PIO executes the read cycle.
• Do not write an address/data to the PIOWRDAT register during write cycle (when the PI-
OSTAT.WBUSY bit = 1) and read cycle (when the PIOSTAT.RBUSY bit = 1).
PiO Read Data Register
Register name
Bit
PIORDDAT
15–8 –
7–0 PRDATA[7:0]
Bits 15–8 Reserved
17-6
Bit name
Initial
0x00
RACC
0
0x00
SFTRST
0
MODEN
0
Bit name
Initial
0x00
0x00
Bit name
Initial
0x00
0x00
Seiko epson Corporation
Reset
R/W
–
R
–
H0
W
Always read as 0.
–
R
–
H0
W
Always read as 0.
H0
R/W
–
Reset
R/W
H0
R/W
–
H0
R/W
Reset
R/W
–
R
–
H0
R
S1C17F13 TeChniCal Manual
Remarks
Remarks
Remarks
(Rev. 1.0)
Advertisement
Table of Contents
