Epson S1C17F13 Technical Manual page 165

16 16-BIT PWM TIMERS (T16A3)
PWM waveform output and normal clock/half-clock mode
By setting the T16AnCCCTL.TOUTAMD[1:0] and/or TOUTBMD[1:0] bits to 0x1, T16A3 generates a PWM
waveform of which the cycle is determined by the compare B signal and the duty ratio is determined by the com-
pare A signal. T16A3 supports half-clock mode to improve the accuracy of the PWM output waveform duty
ratio. In half-clock mode (T16AnCTL.HCM bit = 1), T16A3 uses the dual-edge counter, which counts at the
rising and falling edges of the count clock, to compare with the compare A register. This makes it possible to
control the duty ratio with double accuracy as compared to normal clock mode (T16AnCTL.HCM bit = 0).
Notes: • Be sure to avoid placing T16A3 to half-clock mode under a condition shown below.
(1) When T16A3 is placed into capture mode
(2) When the T16AnCCCTL.TOUTAMD[1:0] or TOUTBMD[1:0] bits are set to 0x2 or 0x3
• The dual-edge counter value cannot be read.
• Do not use the compare A interrupt in half-clock mode.
• In half-clock mode, the T16AnCCB register setting value must be less than [T16AnCCA set-
ting value / 2 + 0x8000].
• The compare B value (T16AnCCB register value) will be compared with the T16AnTC counter
value even if T16A3 Ch.n is set to half-clock mode.
(When T16AnCCCTL.TOUTAMD[1:0] = TOUTBMD[1:0] = 0x1 and T16AnCCCTL.TOUTAINV = TOUTBINV = 0)
Count clock
T16AnTC.T16ATC[15:0]
TOUTAn/TOUTBn
T16AnCCA.CCA[15:0]
Example: T16AnCTL.HCM = 0, T16AnCCA.CCA[15:0] = 1, and T16AnCCB.CCB[15:0] = 5
(When T16AnCCCTL.TOUTAMD[1:0] = TOUTBMD[1:0] = 0x1 and T16AnCCCTL.TOUTAINV = TOUTBINV = 0)
Count clock
T16AnTC.T16ATC[15:0]
TOUTAn/TOUTBn
Figure 16.
(When T16AnCCCTL.TOUTAMD[1:0] = TOUTBMD[1:0] = 0x1 and T16AnCCCTL.TOUTAINV = TOUTBINV = 0)
Count clock
T16AnTC.T16ATC[15:0]
Dual-edge counter
TOUTAn/TOUTBn
T16AnCCA.CCA[15:0]
Example: T16AnCTL.HCM = 1, T16AnCCA.CCA[15:0] = 1, and T16AnCCB.CCB[15:0] = 5
(When T16AnCCCTL.TOUTAMD[1:0] = TOUTBMD[1:0] = 0x1 and T16AnCCCTL.TOUTAINV = TOUTBINV = 0)
Count clock
T16AnTC.T16ATC[15:0]
Dual-edge counter
TOUTAn/TOUTBn
Figure 16.
16-10
n 0 1
0 1
5 0 1
4.4.3 PWM Waveform Output Timings in Normal Clock Mode
n 0 1
2n – 0 1 2
0 1 2
5 0 1
10 – 0 1 2
4.4.4 PWM Waveform Output Timings in Half-Clock Mode
Seiko epson Corporation
2 n-1
2 n-2
2 3 4
2 n-1
3 4 2n-3 2n-2 2n-1
3 4 2n-4 2n-3 2n-2 2n-1
2 3 4
3 4 5 6 7
n 0
n
n-1 (n = T16A CCB.CCB[15:0])
5 0
n 0
2n – 0
n
(n = T16A CCB.CCB[15:0])
5 0
8 9 10 – 0
S1C17F13 TeChniCal Manual
(Rev. 1.0)
1
1
1
1
1
1