Interrupt Controller (Itc); Overview; Vector Table - Epson S1C17F13 Technical Manual

5

Interrupt Controller (ITC)

5.1

Overview

The features of the ITC are listed below.
• Honors interrupt requests from the peripheral circuits and outputs the interrupt request, interrupt level and vector
number signals to the CPU.
• The interrupt level of each interrupt source is selectable from among eight levels.
• Priorities of the simultaneously generated interrupts are established from the interrupt level.
• Handles the simultaneously generated interrupts with the same interrupt level as smaller vector number has high-
er priority.
Figure 5.1.1 shows the configuration of the ITC.
CPU core
5.2

Vector Table

The vector table contains the vectors to the interrupt handler routines (handler routine start address) that will be
read by the CPU to execute the handler when an interrupt occurs.
Table 5.2.1 shows the vector table.
TTBR initial value = 0x8000
Vector number/
Software interrupt Vector address
number
0 (0x00) TTBR + 0x00
1 (0x01) TTBR + 0x04
– (0xfffc00)
2 (0x02) TTBR + 0x08
3 (0x03) TTBR + 0x0c
S1C17F13 TeChniCal Manual
(Rev. 1.0)
ITC
Interrupt request
Interrupt
Interrupt level
control
circuit
Vector number
NMI
Watchdog timer
Figure 5. 1.1 ITC Configuration
Table 5. 2.1 Vector Table
Hardware interrupt name
Reset
Address misaligned interrupt Memory access instruction
Debugging interrupt
NMI
Reserved for C compiler
Seiko epson Corporation
5 INTERRUPT CONTROLLER (ITC)
ILVx[2:0]
ILVy[2:0]
Cause of hardware interrupt
• Low input to the #RESET pin
• Power-on reset
• Brownout reset
• Key entry reset
• Watchdog timer overflow *2
• Supply voltage detector reset
brk instruction, etc.
Watchdog timer overflow *2
–
Peripheral circuit
Interrupt request
Peripheral circuit
Interrupt request
Priority
1
2
3
4
–
5-1