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16 16-BIT PWM TIMERS (T16A3)
T16a3 Comparator/Capture Ch.n Control Register
Register name
Bit
T16AnCCCTL
15–14 CAPBTRG[1:0]
13–12 TOUTBMD[1:0]
11–10 –
9
8
7–6 CAPATRG[1:0]
5–4 TOUTAMD[1:0]
3–2 –
1
0
Bits 15–14 CaPBTRG[1:0]
These bits select the trigger edge(s) of the external signal (CAPBn) at which the counter value is cap-
tured in the T16AnCCB register.
T16AnCCCTL.CAPBTRG[1:0] bits
The T16AnCCCTL.CAPBTRG[1:0] bits are control bits for capture mode and are ineffective in com-
parator mode.
Bits 13–12 TOuTBMD[1:0]
These bits configure how the TOUTB signal waveform (TOUTBn output) is changed by the compare
A and compare B signals. These bits are also used to turn the TOUTB output on and off.
TOUTBMD[1:0] bits
The T16AnCCCTL.TOUTBMD[1:0] bits are control bits for comparator mode and are ineffective in
capture mode.
Bits 11–10 Reserved
Bit 9
TOuTBinV
This bit selects the TOUTB signal (TOUTBn output) polarity.
1 (R/W): Inverted (active low)
0 (R/W): Normal (active high)
The T16AnCCCTL.TOUTBINV bit is a control bit for comparator mode and are ineffective in capture
mode.
Bit 8
CCBMD
This bit selects the T16AnCCB register operating mode.
1 (R/W): Capture mode (T16AnCCB register = capture B register)
0 (R/W): Comparator mode (T16AnCCB register = compare B register)
Bits 7–6
CaPaTRG[1:0]
These bits select the trigger edge(s) of the external signal (CAPAn) at which the counter value is cap-
tured in the T16AnCCA register.
16-14
Bit name
Initial
0x0
0x0
0x0
TOUTBINV
0
CCBMD
0
0x0
0x0
0x0
TOUTAINV
0
CCAMD
0
Table 16.
6.3 Capture B Trigger Edge Selection
0x3
0x2
0x1
0x0
Table 16.
6.4 TOUTB Signal Generation Mode
T16AnCCCTL.
When compare A occurs When compare B occurs
0x3
No change
0x2
0x1
0x0
Seiko epson Corporation
Reset
R/W
H0
R/W
–
H0
R/W
–
R
H0
R/W
H0
R/W
H0
R/W
H0
R/W
–
R
H0
R/W
H0
R/W
Trigger edge
Falling edge and rising edge
Falling edge
Rising edge
Not triggered
Toggle
Toggle
No change
Rise
Fall
Disable output
Remarks
S1C17F13 TeChniCal Manual
(Rev. 1.0)
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