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11 SYNCHRONOUS SERIAL INTERFACE (SPI)
Bit 1
SFTRST
This bit issues software reset to the SPI.
1 (W):
Issue software reset
0 (W):
Ineffective
1 (R):
Software reset is executing.
0 (R):
Software reset has finished. (During normal operation)
Setting this bit resets the SPI shift register and transfer bit counter. This bit is automatically cleared
after the reset processing has finished.
Bit 0
MODen
This bit enables the SPI operations.
1 (R/W): Enable SPI operations (In master mode, the operating clock is supplied.)
0 (R/W): Disable SPI operations (In master mode, the operating clock is stopped.)
Note: If the SPInCTL.MODEN bit is altered from 1 to 0 during sending/receiving data, the data being
sent/received cannot be guaranteed. When setting the SPInCTL.MODEN bit to 1 again after that,
be sure to write 1 to the SPInCTL.SFTRST bit as well.
SPi Ch.n Transmit Data Register
Register name
Bit
SPInTXD
15–8 –
7–0 TXD[7:0]
Bits 15–8 Reserved
Bits 7–0
TXD[7:0]
Data can be written to the transmit data buffer through these bits.
In master mode, writing to these bits starts data transfer.
Transmit data can be written when the SPInINTF.TBEIF bit = 1 regardless of whether data is being
output from the SDOn pin or not.
Note: Be sure to avoid writing to the SPInTXD register when the SPInINTF.TBEIF bit = 0. Otherwise,
transfer data cannot be guaranteed.
SPi Ch.n Receive Data Register
Register name
Bit
SPInRXD
15–8 –
7–0 RXD[7:0]
Bits 15–8 Reserved
Bits 7–0
RXD[7:0]
The receive data buffer can be read through these bits. Received data can be read when the SPInINTF.
RBFIF bit = 1 regardless of whether data is being input from the SDIn pin or not.
Note: The SPInRXD.RXD[7:0] bits are cleared to 0x00 when 1 is written to the SPInCTL.MODEN bit or
the SPInCTL.SFTRST bit.
SPi Ch.n interrupt Flag Register
Register name
Bit
SPInINTF
15–8 –
7–4 –
3
2
1
0
11-12
Bit name
Initial
0x00
0x00
Bit name
Initial
0x00
0x00
Bit name
Initial
0x00
0x0
BSY
0
TENDIF
0
RBFIF
0
TBEIF
1
Seiko epson Corporation
Reset
R/W
–
R
–
H0
R/W
Reset
R/W
–
R
–
H0
R
Reset
R/W
–
R
–
–
R
H0
R
H0/S0
R/W
Cleared by writing 1.
H0/S0
R
Cleared by reading the SPInRXD
register.
H0/S0
R
Cleared by writing to the SPInTXD
register.
Remarks
Remarks
Remarks
S1C17F13 TeChniCal Manual
(Rev. 1.0)
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