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4.3.3
Flash Security Function
This IC provides a security function to protect the internal Flash memory from unauthorized reading and tampering
by using the debugger through ICDmini. Figure 4.3.3.1 shows a Flash security function setting flow.
Factory shipment inspection
Programming with
ROM data and password
IC with protected Flash
Figure 4.
3.3.1 Shipment of IC with ROM Data Programmed and Flash Security Function Setting Flow
The following shows the status of the IC with protected Flash:
• The Flash memory data is undefined if it is read from the debugger.
• An error occurs if an attempt is made to program the Flash memory through ICDmini.
However, the Flash security function can be disabled by entering the unprotecting password predefined to GNU17
IDE (the security function will take effect again after a reset). For setting the password, refer to the "(S1C17 Family
C Compiler Package) S5U1C17001C Manual."
note: Disable the Flash security function before debugging an IC with protected Flash via ICDmini. The
debugging functions may not run normally if the Flash security function is enabled.
4.4
RAM1
RAM1 can be used to execute the instruction codes copied from another memory as well as storing variables or
other data. This allows higher speed processing and lower power consumption than Flash memory. RAM1 can only
be accessed by the CPU.
note: The 64 bytes at the end of RAM1 is reserved as the debug RAM area. When using the debug
functions under application development, do not access this area from the application program.
This area can be used for applications of mass-produced devices that do not need debugging.
The RAM1 size used by the application can be configured to equal or less than the implemented size using the
MSCIRAMSZ.IRAMSZ[2:0] bits. For example, this function can be used to prevent creating programs that seek
to access areas outside the RAM area of the target model when developing an application for a model in which the
RAM size is smaller than this IC. After the limitation is applied, accessing an address outside the RAM1 area results
in the same operation (undefined value is read out) as when a reserved area is accessed.
4.5
RAM2
The embedded RAM2 is used to store display data for the EPD. RAM2 allows the EPD timing controller to read
data as well as accesses from the CPU.
The entire RAM2 area or the area unused for display data can be used as a general-purpose RAM.
4.6
Peripheral Circuit Control Registers
The control registers for the peripheral circuits are located in the 8K-byte area beginning with address 0x4000.
Table 4.6.1 shows the control register map. For details of each control register, refer to "List of Peripheral Circuit
Registers" in the Appendix or "Control Registers" in each peripheral circuit chapter.
S1C17F13 TeChniCal Manual
(Rev. 1.0)
EPSON
Submission
process
Shipment
Seiko epson Corporation
User
Specify the unprotecting password.
Development environment
(6–12 alphanumeric characters (A–Z, a–z, 0–9))
GNU17 IDE
ROM data and password are recorded.
file.PA
Mask data file
4 MEMORY AND BUS
4-3
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