Counter Block Operations - Epson S1C17F13 Technical Manual

16 16-BIT PWM TIMERS (T16A3)
6. Set the following T16AnCTL register bits:
- T16AnCTL.HCM bit
- T16AnCTL.CCABCNT[1:0] bits
- T16AnCTL.CBUFEN bit
- T16AnCTL.TRMD bit
- Set the T16AnCTL.PRESET bit to 1.
- Set the T16AnCTL.MODEN bit to 1.
- Set the T16AnCTL.PRUN bit to 1.
Initial settings for capture mode
1. Configure the T16A3 Ch.n operating clock.
2. Set the T16A0CLK.MULTIMD bit.
3. Set the following T16AnCCCTL register bits:
- Set the T16AnCCCTL.CCAMD bit to 1. * (Set the T16AnCCA register to capture mode)
- Set the T16AnCCCTL.CCBMD bit to 1. * (Set the T16AnCCB register to capture mode)
- T16AnCCCTL.CAPATRG[1:0] bits
- T16AnCCCTL.CAPBTRG[1:0] bits
* One of the T16AnCCA or T16AnCCB register can be set to comparator mode.
4. Set the following bits when using the interrupt:
- Write 1 to the interrupt flags in the T16AnINTF register.
- Set the interrupt enable bits in the T16AnINTE register to 1. (Enable interrupts)
5. Set the following T16AnCTL register bits:
- T16AnCTL.CCABCNT[1:0] bits
- T16AnCTL.TRMD bit
- Set the T16AnCTL.PRESET bit to 1.
- Set the T16AnCTL.MODEN bit to 1.
- Set the T16AnCTL.PRUN bit to 1.
16.4.2

Counter Block Operations

The counter in each counter block channel is a 16-bit up counter that counts the selected operating clock (count
clock).
Counter reset
Setting the T16AnCTL.PRESET bit to 1 clears the counter to 0. In comparator mode, the counter is also cleared
to 0 by the compare B signal (generated when the counter value reaches the T16AnCCB register value).
Counting start
To start counting, set the T16AnCTL.MODEN bit to 1 (start clock supply) and the T16AnCTL.PRUN bit to 1
(start counting). The counting stop control depends on the count mode set.
Count mode (repeat mode and one-shot mode)
Each counter features two count modes: repeat mode and one-shot mode. The count mode can be selected using
the T16AnCTL.TRMD bit.
Repeat mode (T16AnCTL.TRMD bit = 0)
This mode enables the counter to run continuously. Once the count starts, the counter continues running un-
til 0 is written to the T16AnCTL.PRUN bit. The counter continues counting even if the counter returns to 0
due to a counter overflow or by the compare B signal. Select this mode to generate periodic interrupts at de-
sired intervals, to measure pulse width or external event intervals, or to generate a timer output waveform.
One-shot mode (T16AnCTL.TRMD bit = 1)
This mode enables the counter to run for specified periods. The T16AnCTL.PRUN bit is cleared to 0 and
the counter stops automatically as soon as the compare B signal is generated. Select this mode to stop the
counter after an interrupt has occurred once, such as for checking a specific lapse of time.
16-4
(Select half-clock or normal clock mode)
(Select counter channel)
(Enable/disable compare buffer)
(Select one-shot or repeat mode)
(Reset counter)
(Enable count operations)
(Start counting)
(Select multi-comparator/capture or normal channel mode)
(Select capture A trigger edge)
(Select capture B trigger edge)
(Select counter channel)
(Select one-shot or repeat mode)
(Reset counter)
(Enable count operations)
(Start counting)
Seiko epson Corporation
(Clear interrupt flags)
S1C17F13 TeChniCal Manual
(Rev. 1.0)