Epson S1C17F13 Technical Manual page 130

To return a NACK after eight-bit data is received, such as when terminating data reception, write 1 to the
I2CnCTL.TXNACK bit before the data reception is completed. The I2CnCTL.TXNACK bit is automati-
cally cleared to 0 after a NACK has been sent.
STOP/repeated START condition detection
It is the same as the data transmission in slave mode.
Clock stretching by I2C
I 2 C bus S Saddr/W A
BSY = 1
Software bit operations
Operations by the external master
S: START condition, Sr: Repeated START condition, P: STOP condition,
A: ACK, A: NACK, Saddr/W: Slave address + W(0), Data n: 8-bit data
Figure 12.
S1C17F13 TeChniCal Manual
(Rev. 1.0)
STARTIF = 1 RXD[7:0]
Data 1 A
TR = 0 RBFIF = 1
STARTIF = 1 BYTEENDIF = 1
Hardware bit operations
Operations by I2C (slave mode)
4.6.1 Example of Data Receiving Operations in Slave Mode
Data reception
Wait for an interrupt request
(I2CnINTF.STARTIF = 1)
Write 1 to the I2CnINTF.STARTIF bit
Wait for an interrupt request
(I2CnINTF.RBFIF = 1)
Last data received next?
YES
Write 1 to the I2CnCTL.TXNACK bit
Read receive data from the I2CnRXD register
Last data received?
YES
End
Figure 12. 4.6.2 Slave Mode Data Reception Flowchart
Seiko epson Corporation
→
Data 1 RXD[7:0]
Data 2 A
RBFIF = 1
BYTEENDIF = 1
TXNACK = 1
RXD[7:0]
A
RBFIF = 1
BYTEENDIF = 1
NO
NO
12 I 2 C (I2C)
→ →
Data (N -1) RXD[7:0]
Data N A P
RBFIF = 1 BSY = 0
BYTEENDIF = 1 STOPIF = 1
Sr
→ →
Data (N -1) RXD[7:0]
Data N A P
RBFIF = 1 BSY = 0
BYTEENDIF = 1 TXNACK = 0
STOPIF = 1
Sr
TXNACK = 0
Data N
Data N
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