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Bit 11
SCllOW
This bit indicates that SCL is set to low level.
1 (R):
SCL = Low level
0 (R):
SCL = High level
Bit 10
BSY
This bit indicates that the I
1 (R):
I
2
0 (R):
I
2
Bit 9
TR
This bit indicates whether the I2C is set in transmission mode or not.
1 (R):
Transmission mode
0 (R):
Reception mode
Bit 8
Reserved
Bit 7
BYTeenDiF
Bit 6
GCiF
Bit 5
naCKiF
Bit 4
STOPiF
Bit 3
STaRTiF
Bit 2
eRRiF
Bit 1
RBFiF
Bit 0
TBeiF
These bits indicate the I2C interrupt cause occurrence status.
1 (R):
Cause of interrupt occurred
0 (R):
No cause of interrupt occurred
1 (W):
Clear flag
0 (W):
Ineffective
The following shows the correspondence between the bit and interrupt:
I2CnINTF.BYTEENDIF bit: End of transfer interrupt
I2CnINTF.GCIF bit:
I2CnINTF.NACKIF bit:
I2CnINTF.STOPIF bit:
I2CnINTF.STARTIF bit:
I2CnINTF.ERRIF bit:
I2CnINTF.RBFIF bit:
I2CnINTF.TBEIF bit:
i2C Ch.n interrupt enable Register
Register name
Bit
I2CnINTE
15–8 –
7
6
5
4
3
2
1
0
Bits 15–8 Reserved
S1C17F13 TeChniCal Manual
(Rev. 1.0)
2
C bus is placed into busy status.
C bus busy
C bus free
General call address reception interrupt
NACK reception interrupt
STOP condition interrupt
START condition interrupt
Error detection interrupt
Receive buffer full interrupt
Transmit buffer empty interrupt
Bit name
Initial
0x00
BYTEENDIE
GCIE
NACKIE
STOPIE
STARTIE
ERRIE
RBFIE
TBEIE
Seiko epson Corporation
Reset
R/W
–
R
–
0
H0
R/W
0
H0
R/W
0
H0
R/W
0
H0
R/W
0
H0
R/W
0
H0
R/W
0
H0
R/W
0
H0
R/W
12 I
2
C (I2C)
Remarks
12-21
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