Pd Port Group; Common Registers Between Port Groups - Epson S1C17F13 Technical Manual

Cmos 16-bit single chip microcontroller
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6.7.6

Pd Port Group

The Pd port group consists of three ports Pd0–Pd2 and they are configured as a debugging function port at ini-
tialization. These three ports support the GPIO function. The GPIO function of the Pd2 port supports output only,
therefore, the pull-up/down function cannot be used.
Register name
Bit
PDDAT
15–11 –
(Pd Port Data
10–8 PDOUT[2:0]
Register)
7–2 –
1–0 PDIN[1:0]
PDIOEN
15–11 –
(Pd Port Enable
10
Register)
9–8 PDIEN[1:0]
7–3 –
2
1–0 PDOEN[1:0]
PDRCTL
15–11 –
(Pd Port Pull-up/
10
down Control Regis-
9–8 PDPDPU[1:0]
ter)
7–3 –
2
1–0 PDREN[1:0]
PDINTF
15–0 –
PDINTCTL
PDCHATEN
PDMODSEL
15–8 –
(Pd Port Mode Select
7–3 –
Register)
2–0 PDSEL[2:0]
PDFNCSEL
15–8 –
(Pd Port Function
7–6 –
Select Register)
5–4 PD2MUX[1:0]
3–2 PD1MUX[1:0]
1–0 PD0MUX[1:0]
PdSELy = 0
Port name
GPIO
Peripheral
Pd0
Pd0
DBG
Pd1
Pd1
DBG
Pd2
Pd2
DBG
6.7.7

Common Registers between Port Groups

Table 6.
Register name
Bit
PCLK
15–9 –
(P Port Clock Control
8
Register)
7–4 CLKDIV[3:0]
3–2 KRSTCFG[1:0]
1–0 CLKSRC[1:0]
PINTFGRP
15–8 –
(P Port Interrupt Flag
7–2 –
Group Register)
1
0
S1C17F13 TeChniCal Manual
(Rev. 1.0)
Table 6.
7.6.1 Control Registers for Pd Port Group
Bit name
Initial
0x00
0x0
0x00
x
0x00
reserved
0
0x0
0x00
reserved
0
0x0
0x00
reserved
0
0x0
0x00
reserved
0
0x0
0x0000
0x00
0x00
0x7
0x00
0x0
0x0
0x0
0x0
Table 6.
7.6.2 Pd Port Group Function Assignment
PdyMUX = 0x0
PdyMUX = 0x1
(Function 0)
(Function 1)
Pin
Peripheral
DST2
DSIO
DCLK
7.7.1 Control Registers for Common Use with Port Groups
Bit name
Initial
0x00
DBRUN
0
0x0
0x0
0x0
0x00
0x00
P1INT
0
P0INT
0
Seiko epson Corporation
Reset
R/W
R
H0
R/W
R
H0
R
R
H0
R/W
H0
R/W
R
H0
R/W
H0
R/W
R
H0
R/W
H0
R/W
R
H0
R/W
H0
R/W
R
R
R
H0
R/W
R
R
H0
R/W
Valid settings: 0x0
H0
R/W
H0
R/W
PdSELy = 1
PdyMUX = 0x2
(Function 2)
Pin
Peripheral
Pin
Reset
R/W
R
H0
R/WP
H0
R/WP
H0
R/WP
H0
R/WP
R
R
H0
R
H0
R
6 I/O PORTS (PPORT)
Remarks
PdyMUX = 0x3
(Function 3)
Peripheral
Pin
Remarks
6-15

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