T16A3 Counter Ch.n Data Register - Epson S1C17F13 Technical Manual

Bits 5–4 CCaBCnT[1:0]
These bits select a counter to be connected to the comparator/capture block of each channel in multi-
comparator/capture mode (T16A0CLK.MULTIMD bit = 1).
When using T16A3 in normal channel mode (T16A0CLK.MULTIMD bit = 0), be sure to connect the
counter of the same channel to each comparator/capture block.
Bit 3 CBuFen
This bit enables or disables the compare buffers.
1 (R/W): Enable
0 (R/W): Disable
For detailed information, refer to "Comparator/Capture Block Operations, Compare buffers."
Note: Make sure the counter is halted (T16AnCTL.PRUN bit = 0) before setting the T16AnCTL.
CBUFEN bit.
Bit 2 TRMD
This bit selects the count mode.
1 (R/W): One-shot mode
0 (R/W): Repeat mode
For detailed information, refer to "Counter Block Operations, Count mode (repeat mode and one-shot
mode)."
Bit 1 PReSeT
This bit resets the counter.
1 (W): Reset
0 (W): Ineffective
1 (R): Resetting in progress
0 (R): Resetting finished or normal operation
Writing 1 to this bit clears the counter to 0.
Bit 0 MODen
This bit enables the T16A3 Ch.n operations.
1 (R/W): Enable (Start supplying operating clock)
0 (R/W): Disable (Stop supplying operating clock)

T16a3 Counter Ch.n Data Register

Register name Bit
T16AnTC 15–0 T16ATC[15:0]
Bits 15–0 T16aTC[15:0]
The current counter value can be read out through these bits.
S1C17F13 TeChniCal Manual
(Rev. 1.0)
Table 16. 6.2 Counter Selection
T16AnCTL.CCABCNT[1:0] bits
0x3
0x2
0x1
0x0
Bit name Initial
0x0000
Seiko epson Corporation
16 16-BIT PWM TIMERS (T16A3)
Counter channel
Counter block Ch.3
Counter block Ch.2
Counter block Ch.1
Counter block Ch.0
Reset R/W
H0 R –
Remarks
16-13