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7 WATCHDOG TIMER (WDT)
Bit 8
STaTnMi
This bit indicates that a counter overflow and NMI have occurred.
1 (R):
NMI (counter overflow) occurred
0 (R):
NMI not occurred
When the NMI generation function of WDT is used, read this bit in the NMI handler routine to con-
firm that WDT was the source of the NMI.
The STATNMI set to 1 is cleared to 0 by resetting WDT.
Bits 7–5
Reserved
Bit 4
WDTCnTRST
This bit resets WDT.
1 (WP):
Reset
0 (WP):
Ignored
0 (R):
Always 0 when being read
Bits 3–0
WDTRun[3:0]
These bits control WDT to run and stop.
0xa (R/WP):
Values other than 0xa (R/WP): Run
Always 0x0 is read if a value other than 0xa is written.
Since an NMI or reset may be generated immediately after running depending on the counter value,
WDT should also be reset concurrently when running WDT.
7-4
Stop
Seiko epson Corporation
S1C17F13 TeChniCal Manual
(Rev. 1.0)
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