Data Reception In Slave Mode - Epson S1C17F13 Technical Manual

12 I 2 C (I2C)
(I2CnINTF.TBEIF = 1 or I2CnINTF.NACKIF = 1)
12.4.6

Data Reception in Slave Mode

A data receiving procedure in slave mode and the I2C Ch.n operations are shown below. Figures 12.4.6.1 and 12.4.6.2
show an operation example and a flowchart, respectively.
Data receiving procedure
1. Wait for a START condition interrupt (I2CnINTF.STARTIF bit = 1).
2. Check to see if the I2CnINTF.TR bit = 0 (reception mode).
(Start a data sending procedure if I2CnINTF.TR bit = 1.)
3. Clear the I2CnINTF.STARTIF bit by writing 1.
4. Wait for a receive buffer full interrupt (I2CnINTF.RBFIF bit = 1) generated when a one-byte reception has
completed or an end of transfer interrupt (I2CnINTF.BYTEENDIF bit = 1).
Clear the I2CnINTF.BYTEENDIF bit by writing 1 after the interrupt has occurred.
5. If the next receive data is the last one, write 1 to the I2CnCTL.TXNACK bit to send a NACK after it is re-
ceived.
6. Read the received data from the I2CnRXD register.
7. Repeat Steps 4 to 6 until the end of data reception.
Data receiving operations
START condition detection and slave address check
It is the same as the data transmission in slave mode.
However, the I2CnINTF.TR bit is cleared to 0 and the I2CnINTF.TBEIF bit is not set.
If the I2CnMOD.GCEN bit is set to 1 (general call address response enabled), the I2C Ch.n starts data re-
ceiving operations when the general call address is received.
Slave mode can be operated even in SLEEP mode, it makes it possible to wake the CPU up using an inter-
rupt when an address match is detected.
Receiving the first data byte
After the valid slave address has been received, the I2C Ch.n sends an ACK and pulls down SCL to low un-
til 1 is written to the I2CnINTF.STARTIF bit. This puts the I
nal master into standby state. When 1 is written to the I2CnINTF.STARTIF bit, the I2C Ch.n releases SCL
and receives data sent from the external master into the shift register. After eight-bit data has been received,
the I2C Ch.n sends an ACK and pulls down SCL to low. The received data in the shift register is transferred
to the receive data buffer and the I2CnINTF.RBFIF and I2CnINTF.BYTEENDIF bits are both set to 1. Af-
ter that, the received data can be read out from the I2CnRXD register.
Receiving subsequent data
When the received data is read out from the I2CnRXD register after the I2CnINTF.RBFIF bit has been set to 1,
the I2C Ch.n clears the I2CnINTF.RBFIF bit to 0, releases SCL, and receives subsequent data sent from the
external master. After eight-bit data has been received, the I2C Ch.n sends an ACK and pulls down SCL to
low. The received data in the shift register is transferred to the receive data buffer and the I2CnINTF.RBFIF
and I2CnINTF.BYTEENDIF bits are both set to 1.
12-12
Data transmission
Wait for an interrupt request
I2CnINTF.NACKIF = 1 ?
YES
Write data to the I2CnTXD register
End
Figure 12. 4.5.2 Slave Mode Data Transmission Flowchart
Seiko epson Corporation
NO
2 C bus into clock stretching state and the exter-
S1C17F13 TeChniCal Manual
(Rev. 1.0)