Epson S1C17F13 Technical Manual page 204

Cmos 16-bit single chip microcontroller
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Mode set-
Instruction
ting value
0x00
0x01
ld.cf %rd,%rs
(ext
imm9)
ld.cf %rd,imm7
0x02
ld.cf %rd,%rs
(ext
imm9)
ld.cf %rd,imm7
S1C17 Core
Mode set-
Instruction
ting value
0x07
ld.ca %rd,%rs
(ext
imm9)
ld.ca %rd,imm7
0x17
ld.ca %rd,%rs
(ext
imm9)
ld.ca %rd,imm7
Example:
ld.cw %r0,0x0
ld.cw %r0,0x7
ld.ca %r0,%r1
ld.cw %r0,0x13 ; Sets the mode (operation result read mode and 16 high-order bits output mode).
ld.ca %r1,%r0
Conditions to set the overflow (V) flag
An overflow occurs in a MAC operation and the overflow (V) flag is set to 1 when the signs of the multiplica-
tion result, operation result register value, and multiplication & accumulation result match the following condi-
tions:
S1C17F13 TeChniCal Manual
(Rev. 1.0)
Table 21.
5.1 Initializing the Operation Result Register
Operations
res[31:0] ← 0x0
res[31:16] ← 0x0
res[15:0] ← %rs
res[31:16] ← 0x0
res[15:0] ← imm7/16
res[31:16] ← %rd
res[15:0] ← %rs
res[31:16] ← %rd
res[15:0] ← imm7/16
Argument 2
Argument 1
Coprocessor
output (16 bits)
Flag output
Figure 21.
5.2 Data Path in MAC Mode
Table 21.
5.2 Operation in MAC Mode
Operations
res[31:0] ← %rd × %rs + res[31:0]
%rd ← res[15:0]
res[31:0] ← %rd × imm7/16 +
res[31:0]
%rd ← res[15:0]
res[31:0] ← %rd × %rs + res[31:0]
%rd ← res[31:16]
res[31:0] ← %rd × imm7/16 +
res[31:0]
%rd ← res[31:16]
; Sets the mode (initialize mode 0).
; Sets the mode (signed MAC mode and 16 low-order bits output mode).
; Performs "res = %r0 × %r1 + res" and loads the 16 low-order bits of the result to %r0.
; Loads the 16 high-order bits of the result to %r1.
Seiko epson Corporation
Setting the operating mode executes the initialization with-
out sending data.
COPRO
16 bits
32 bits
Operation
result
Operation result
register
Selector
Flags
psr (CVZN) ← 0b0100
if an overflow has oc-
curred
Otherwise
psr (CVZN) ← 0b0000
21 Multiplier/Divider (COPRO)
Remarks
res: operation result register
32 bits
Remarks
The operation result
register keeps the
operation result un-
til it is rewritten by
other operation.
res: operation result register
21-5

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