Uart Ch.n Mode Register - Epson S1C17F13 Technical Manual

Bits 15–9 Reserved
Bit 8 DBRun
This bit sets whether the UART operating clock is supplied in DEBUG mode or not.
1 (R/W): Clock supplied in DEBUG mode
0 (R/W): No clock supplied in DEBUG mode
Bits 7–6 Reserved
Bits 5–4 ClKDiV[1:0]
These bits select the division ratio of the UART operating clock.
Bits 3–2 Reserved
Bits 1–0 ClKSRC[1:0]
These bits select the clock source of the UART.
UAnCLK.
CLKDIV[1:0] bits
0x3
0x2
0x1
0x0
(Note) The oscillation circuits/external input that are not supported in this IC cannot be
selected as the clock source.
Note: The UAnCLK register settings can be altered only when the UAnCTL.MODEN bit = 0.

uaRT Ch.n Mode Register

Register name Bit
UAnMOD 15–10 –
9
8
7
6
5
4
3
2
1
0
Bits 15–10 Reserved
Bit 9 inViRRX
This bit enables the USINn input inverting function when the IrDA interface function is enabled.
1 (R/W): Enable input inverting function
0 (R/W): Disable input inverting function
Bit 8 inViRTX
This bit enables the USOUTn output inverting function when the IrDA interface function is enabled.
1 (R/W): Enable output inverting function
0 (R/W): Disable output inverting function
Bit 7 Reserved
Bit 6 Puen
This bit enables pull-up of the USINn pin.
1 (R/W): Enable pull-up
0 (R/W): Disable pull-up
S1C17F13 TeChniCal Manual
(Rev. 1.0)
Table 10. 8.1 Clock Source and Division Ratio Settings
0x0
OSC3B
1/8
1/4
1/2
1/1
Bit name Initial
0x00
INVIRRX 0
INVIRTX 0
– 0
PUEN 0
OUTMD 0
IRMD 0
CHLN 0
PREN 0
PRMD 0
STPB 0
Seiko epson Corporation
UAnCLK.CLKSRC[1:0] bits
0x1 0x2
OSC1 OSC3A
1/1 1/8
1/4
1/2
1/1
Reset R/W
– R –
H0 R/W
H0 R/W
– R
H0 R/W
H0 R/W
H0 R/W
H0 R/W
H0 R/W
H0 R/W
H0 R/W
10 UART (UART)
0x3
EXOSC
1/1
Remarks
10-9