Operations In Gpio Mode - Epson S1C17F13 Technical Manual

17 Parallel Interface (PIO)
Data read operations
Writing 1 to the PIOCTL.RACC bit generates a trigger signal and it is sampled within one CLK_PIO clock
cycle. This starts a data read cycle.
After one clock cycle from the trigger sampling, PIO asserts the #PIOCE signal and outputs the address from
the PIOA[7:0] pins. The PIOSTAT.RBUSY bit is also set to 1 (read cycle busy status).
PIO asserts the #PIORD signal while the access cycle (one CLK_PIO clock cycle) to input data from the
PIOD[7:0] pins to after the setup cycle (one CLK_PIO clock cycle). The input data is loaded to the PIORDDAT.
PRDATA[7:0] bits.
PIO negates the #PIOCE signal after the hold cycle (one CLK_PIO clock cycle).
Finally, PIO clears the PIOSTAT.RBUSY bit to 0 (read cycle completed/idle status).
Trigger signal
PIORDDAT.PRDATA[7:0]
PIOSTAT.RBUSY
17.4.3

Operations in GPIO Mode

In GPIO mode (PIOMOD.GPIOMD bit = 1), the address bus pins and data bus pins are configured as eight bits of
general-purpose output ports and eight bits of general-purpose input ports, respectively. The bus control signals are
always fixed at inactive state and the PIOWRDAT.PWDATA[7:0] bits become ineffective.
Port output
Write data to be output from the PIOA[7:0] pins to the PIOWRDAT.PADDR[7:0] bits.
The PIOA[7:0] pin outputs change immediately after writing.
Port input
The PIOD[7:0] pin status can be read through the PIORDDAT.PRDATA[7:0] bits.
The PIOD[7:0] pin status is sampled in the CLK_PIO clock cycles and loaded to the PIORDDAT.PRDATA[7:0]
bits. Therefore, maximum one CLK_PIO cycle of delay occurs until the input transition is reflected to the PI-
ORDDAT.PRDATA[7:0] bits.
17-4
PIOCTL.RACC = 1
Sampling & clear
CLK_PIO
#PIOCE
#PIORD
PIOA[7:0]
PIOD[7:0]
State
Idle
Figure 17. 4.2.2 Data Read Timing
Seiko epson Corporation
PIOWRDAT.PADDR[7:0]
Setup Access Hold
S1C17F13 TeChniCal Manual
Idle
(Rev. 1.0)