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4 MEMORY AND BUS
FlaShC Flash Read Cycle Register
Register name
Bit
FLASHCWAIT
15–8 –
7
6–2 –
1–0 RDWAIT[1:0]
Bits 15–8 Reserved
Bit 7
XBuSY
This bit indicates whether the Flash memory can be accessed or not.
1 (R):
Flash memory ready to access
0 (R):
Flash access prohibited
The Flash memory can always be accessed during normal operation.
Bits 6–2
Reserved
Bits 1–0
RDWaiT[1:0]
These bits set the number of bus access cycles for reading from the Flash memory.
Table 4.
FLASHCWAIT.RDWAIT[1:0] bits Number of bus access cycles
note: Be sure to set the FLASHCWAIT.RDWAIT[1:0] bits before the system clock is configured.
4-8
Table 4.
7.1 Internal RAM Size Selections
MSCIRAMSZ.IRAMSZ[2:0] bits
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
Bit name
Initial
0x00
XBUSY
0x00
0x0
7.2 Setting Number of Bus Access Cycles for Flash Read
0x3
0x2
0x1
0x0
Seiko epson Corporation
Internal RAM size
Reserved
(16KB)*
(12KB)*
6KB
4KB
2KB
1KB
512B
* Setting prohibited in this IC
Reset
R/W
–
R
–
0
H0
R
–
R
H0
R/WP
System clock frequency
4
3
2
1
Remarks
20.0 MHz (max.)
20.0 MHz (max.)
16.3 MHz (max.)
8.2 MHz (max.)
S1C17F13 TeChniCal Manual
(Rev. 1.0)
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