Table Of Contents - Epson S1C17F13 Technical Manual

Cmos 16-bit single chip microcontroller
Table of Contents

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Configuration of product number..............................................................................................i
Preface ..................................................................................................................................... ii
Notational conventions and symbols in this manual ............................................................... ii
1 Overview ........................................................................................................................1-1
1.1 Features .......................................................................................................................... 1-1
1.2 Block Diagram ................................................................................................................. 1-3
1.3 Pins ................................................................................................................................. 1-4
1.3.1 Pin Configuration Diagram (TQFP13-64pin) ..................................................... 1-4
1.3.2 Pad Configuration Diagram (Chip) .................................................................... 1-5
1.3.3 Pin Descriptions ................................................................................................ 1-6
2 Power Supply, Reset, and Clocks ...............................................................................2-1
2.1 Power Generator (PWG) .................................................................................................. 2-1
2.1.1 Overview ........................................................................................................... 2-1
2.1.2 Pins ................................................................................................................... 2-2
2.2 System Reset Controller (SRC) ....................................................................................... 2-2
2.2.1 Overview ........................................................................................................... 2-2
2.2.2 Input Pin ............................................................................................................ 2-3
2.2.3 Reset Sources .................................................................................................. 2-3
2.2.4 Initialization Conditions (Reset Groups) ............................................................ 2-4
2.3 Clock Generator (CLG) .................................................................................................... 2-5
2.3.1 Overview ........................................................................................................... 2-5
2.3.2 Input/Output Pins ............................................................................................. 2-6
2.3.3 Clock Sources .................................................................................................. 2-6
2.3.4 Operations ........................................................................................................ 2-8
2.4 Operating Mode ............................................................................................................. 2-11
2.4.1 Initial Boot Sequence ....................................................................................... 2-11
2.4.2 Transition between Operating Modes .............................................................. 2-11
2.5 Interrupts ........................................................................................................................ 2-12
2.6 Control Registers ........................................................................................................... 2-13
CLG System Clock Control Register ........................................................................................ 2-13
CLG Oscillation Control Register ............................................................................................. 2-14
CLG OSC3B Control Register .................................................................................................. 2-15
CLG OSC1 Control Register .................................................................................................... 2-15
CLG OSC3A Control Register .................................................................................................. 2-16
CLG Interrupt Flag Register ..................................................................................................... 2-16
CLG Interrupt Enable Register ................................................................................................. 2-17
CLG FOUT Control Register ..................................................................................................... 2-17
3 CPU and Debugger ......................................................................................................3-1
3.1 Overview ......................................................................................................................... 3-1
3.2 CPU Core ........................................................................................................................ 3-2
3.2.1 CPU Registers .................................................................................................. 3-2
3.2.2 Instruction Set .................................................................................................. 3-2
3.2.3 Reading PSR .................................................................................................... 3-2
3.2.4 I/O Area Reserved for the S1C17 Core ............................................................ 3-2
S1C17F13 TeChniCal Manual
(Rev. 1.0)
- Contents -
Regulator .................................................................................................... 2-2
Regulator .................................................................................................. 2-2
Regulator Control Register ....................................................................................... 2-13
Seiko epson Corporation
) ........................................................... 2-2
PP
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