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8 SUPPLY VOLTAGE DETECTOR (SVD)
8.2
Input Pin and External Connection
8.2.1
Input Pin
Table 8.2.1.1 shows the SVD input pin.
Pin name
EXSVD
If the port is shared with the EXSVD pin and other functions, the EXSVD function must be assigned to the port be-
fore SVD can be activated. For more information, refer to the "I/O Ports" chapter.
8.2.2
External Connection
Figure 8.
For the EXSVD pin input voltage range, refer to "Supply Voltage Detector Characteristics, EXSVD pin input volt-
age range V
" in the "Electrical Characteristics" chapter.
EXSVD
8.3
Clock Settings
8.3.1
SVD Operating Clock
When using SVD, the SVD operating clock CLK_SVD must be supplied to SVD from the clock generator.
The CLK_SVD supply should be controlled as in the procedure shown below.
1. Write 0x0096 to the MSCPROT.PROT[15:0] bits. (Remove system protection)
2. Enable the clock source in the clock generator if it is stopped (refer to "Clock Generator" in the "Power Supply,
Reset, and Clocks" chapter).
3. Set the following SVDCLK register bits:
- SVDCLK.CLKSRC[1:0] bits
- SVDCLK.CLKDIV[2:0] bits
4. Write a value other than 0x0096 to the MSCPROT.PROT[15:0] bits. (Set system protection)
The CLK_SVD frequency should be set to around 32 kHz.
8.3.2
Clock Supply in SLEEP Mode
When using SVD during SLEEP mode, the SVD operating clock CLK_SVD must be configured so that it will
keep supplying by writing 0 to the CLGOSC.xxxxSLPC bit for the CLK_SVD clock source.
If the CLGOSC.xxxxSLPC bit for the CLK_SVD clock source is 1, the CLK_SVD clock source is deactivated dur-
ing SLEEP mode and SVD stops with the register settings maintained at those before entering SLEEP mode. After
the CPU returns to normal mode, CLK_SVD is supplied and the SVD operation resumes.
8-2
Table 8.
2.1.1 SVD Input Pin
I/O*
Initial status*
A
A (Hi-Z)
External power
EXSVD
supply/regulator
etc.
2.2.1 Connection between EXSVD Pin and External Power Supply
Seiko epson Corporation
External power supply voltage detection pin
* Indicates the status when the pin is configured for SVD.
SVD
SVD
analog block
(Clock source selection)
(Clock division ratio selection = Clock frequency setting)
Function
S1C17F13 TeChniCal Manual
(Rev. 1.0)
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