Error Detection - Epson S1C17F13 Technical Manual

Normal operations
SDA
SCL
When SDA = LOW is detected
SDA
SCL
SDA
SCL
12.4.9

Error Detection

The I2C includes a hardware error detection function.
Furthermore, the I2CnINTF.SDALOW and I2CnINTF.SCLLOW bits are provided to allow software to check whether
the SDA and SCL lines are fixed at low. If unintended low level is detected on SDA or SCL, a software recovery pro-
cessing, such as I2C Ch.n software reset, can be performed.
The table below lists the hardware error detection conditions and the notification method.
No. Error detecting period/timing
1 While the I2C Ch.n controls SDA to high for sending address,
data, or a NACK
2 <Master mode only> When 1 is written to the I2CnCTL.TX-
START bit while the I2CnINTF.BSY bit = 0
3 <Master mode only> When 1 is written to the I2CnCTL.TXS-
TOP bit while the I2CnINTF.BSY bit = 0
4 <Master mode only> When 1 is written to the I2CnCTL.TX-
START bit while the I2CnINTF.BSY bit = 0 (Refer to "Automatic
Bus Clearing Operation.")
S1C17F13 TeChniCal Manual
(Rev. 1.0)
START
condition
SDA check
1 2
SDA check (n
Bus clearing operation
1 2
Figure 12. 4.8.1 Automatic Bus Clearing Operation
Table 12. 4.9.1 Hardware Error Detection Function
Seiko epson Corporation
Slave address + R/W
START
condition
n
≤
9)
STARTIF = 1
10
STARTIF = 1
ERRIF = 1
I C bus line monitored and
2
error condition
SDA = low
SCL = low
SCL = low
SDA
Automatic bus clearing
failure
12 I 2 C (I2C)
Notification method
I2CnINTF.ERRIF = 1
I2CnINTF.ERRIF = 1
I2CnCTL.TXSTART = 0
I2CnINTF.STARTIF = 1
I2CnINTF.ERRIF = 1
I2CnCTL.TXSTOP = 0
I2CnINTF.STOPIF = 1
I2CnINTF.ERRIF = 1
I2CnCTL.TXSTART = 0
I2CnINTF.STARTIF = 1
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