Control Registers; I2C Ch.n Clock Control Register - Epson S1C17F13 Technical Manual

(2) STOP condition interrupt
Master mode
Slave mode
(f : I2C operating clock frequency [Hz], BRT: I2CnBR.BRT[6:0] bits setting value (1 to 127))
CLK_I2Cn
12.6

Control Registers

i2C Ch.n Clock Control Register

Register name Bit
I2CnCLK 15–9 –
8
7–6 –
5–4 CLKDIV[1:0]
3–2 –
1–0 CLKSRC[1:0]
Bits 15–9 Reserved
Bit 8 DBRun
This bit sets whether the I2C operating clock is supplied in DEBUG mode or not.
1 (R/W): Clock supplied in DEBUG mode
0 (R/W): No clock supplied in DEBUG mode
Bits 7–6 Reserved
Bits 5–4 ClKDiV[1:0]
These bits select the division ratio of the I2C operating clock.
Bits 3–2 Reserved
Bits 1–0 ClKSRC[1:0]
These bits select the clock source of the I2C.
I2CnCLK.
CLKDIV[1:0] bits
0x3
0x2
0x1
0x0
(Note) The oscillation circuits/external input that are not supported in this IC cannot be
selected as the clock source.
Note: The I2CnCLK register settings can be altered only when the I2CnCTL.MODEN bit = 0.
S1C17F13 TeChniCal Manual
(Rev. 1.0)
SDA
SCL
TXSTOP = 1
RXD[7:0] read (during reception)
SDA
SCL
Figure 12. 5.1 START/STOP Condition Interrupt Timings
Bit name Initial
0x00
DBRUN 0
0x0
0x0
0x0
0x0
Table 12. 6.1 Clock Source and Division Ratio Settings
0x0
OSC3B
1/8
1/4
1/2
1/1
Seiko epson Corporation
(BRT + 3) × 3
f
CLK_I2Cn
TXSTOP = 0
STOPIF = 1
BSY = 0
STOPIF = 1
Reset R/W
– R –
H0 R/W
– R
H0 R/W
– R
H0 R/W
I2CnCLK.CLKSRC[1:0] bits
0x1 0x2
OSC1 OSC3A
1/1 1/8
1/4
1/2
1/1
12 I 2 C (I2C)
Remarks
0x3
EXOSC
1/1
12-17