Overview; Features - Epson S1C17F13 Technical Manual

1

Overview

The S1C17F13 is an ultra low-power MCU equipped with a display memory and an EPD timing controller to send
display data for using the active EPD panels. This IC includes the synchronous serial interface, parallel interface,
UART, and I 2 C to communicate with an EPD panel and other devices. This IC allows measurement of various envi-
ronmental conditions such as a temperature and humidity measurement using the R/F converter, and a supply volt-
age measurement using the supply voltage detector and brownout reset circuits.
1.1

Features

Model
CPU
CPU core
Multiplier/Divider (COPRO)
Other
Embedded Flash memory
Capacity
Erase/program count
Other
Embedded RAM
Capacity
Clock generator (CLG)
System clock source
System clock frequency (operating frequency) 20 MHz (max.)
OSC3B internal high-speed oscillator circuit
(boot clock source)
OSC1B internal low-speed oscillator circuit
OSC3A high-speed oscillator circuit
OSC1A low-speed oscillator circuit
EXOSC clock input
Other
I/O port (PPORT)
Number of general-purpose I/O ports
Number of input interrupt ports
Other
Display control
EPD timing controller (EPD Tcon)
Communication interfaces
UART (UART)
Synchronous serial interface (SPI)
I C (I2C)
2
Parallel interface (PIO)
S1C17F13 TeChniCal Manual
(Rev. 1.0)
Table 1. 1.1 Features
Seiko Epson original 16-bit RISC CPU core S1C17
16-bit × 16-bit multiplier
16-bit × 16-bit + 32-bit multiply and accumulation unit
16-bit ÷ 16-bit divider
On-chip debugger
128K bytes (for both instructions and data) *1
50 times (min.) * Programming by the debugging tool ICDmini
Security function to protect from reading/programming by ICDmini
On-board programming function using ICDmini
Embedded Flash voltage booster to generate the Flash erasing/programming voltage
6K bytes (area accessed by CPU only)
14K bytes (area accessed by CPU and EPD Tcon)
5 sources (OSC3B, OSC3A, OSC1B, OSC1A, and EXOSC)
20/16/12/8 MHz (typ.) selectable via software
32 kHz (typ.)
20 MHz (max.) crystal or ceramic oscillator circuit
32.768 kHz (typ.) crystal oscillator circuit
20 MHz (max.) square or sine wave input
Configurable system clock division ratio
Configurable system clock (except for OSC1A and OSC1B) used at wake up from
SLEEP state
Operating clock frequency for the CPU and all peripheral circuits is selectable.
37 bits (max.) (Pins are shared with the peripheral I/O.)
8 bits
All pins contain a pull-up/down resistor that can be enabled/disabled via software.
16 bits contain an interrupt function and a chattering filter function.
Controls display on the active-matrix EPD via the embedded SPI or PIO.
Includes a display data read function from the embedded RAM (area for both CPU
and EPD Tcon).
Can be controlled with the dedicated API library.
1 channel
IrDA1.0 supported
Embedded baud-rate generator
3 channels
Configurable as the communication interface for EPD Tcon (SPI Ch.1)
1 channel
Master and slave operations supported
Embedded baud-rate generator
Address length: 8 bits (max.)
Data width: 8 bits (max.)
Control signals: #CE, #RD, #WR
Configurable as the communication interface for EPD Tcon
Seiko epson Corporation
S1C17F13
1 OVERVIEW
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