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12 I
2
C (I2C)
Standby state (SCL = low)
TXSTART = 1
Saddr/R
→
TXD[7:0]
I
2
C bus
S
Saddr/R
TXSTART = 0
STARTIF = 1
TBEIF = 1
NACKIF = 1
NACKIF = 1
NACKIF = 1
Figure 12.
Write 1 to the I2CnCTL.TXNACK bit
Read receive data from the I2CnRXD register
12-8
RXD[7:0]
A
Data 1
A
Data 2
RBFIF = 1
TXSTOP = 1
A
P
TXSTOP = 0
STOPIF = 1
TXSTART = 1
A
Sr
TXSTART = 0
STARTIF = 1
TBEIF = 1
TXSTART = 1
TXSTOP = 1
A
P
S
TXSTART = 0
STARTIF = 1
TXSTOP = 0
TBEIF = 1
STOPIF = 1
4.3.1 Example of Data Receiving Operations in Master Mode
Data reception
Write 1 to the I2CnCTL.TXSTART bit
Wait for an interrupt request
(I2CnINTF.TBEIF = 1)
Write slave address and READ(1) to
the I2CnTXD register
Wait for an interrupt request
(I2CnINTF.RBFIF = 1 or I2CnINTF.NACKIF = 1)
I2CnINTF.RBFIF = 1 ?
YES
Receive last data next?
NO
Last data received?
Read receive data from the I2CnRXD register
Write 1 to the I2CnCTL.TXSTOP bit
Wait for an interrupt request
(I2CnINTF.STOPIF = 1)
Figure 12.
4.3.2 Master Mode Data Reception Flowchart
Seiko epson Corporation
TXNACK = 1
→
Data 1
RXD[7:0]
A
RBFIF = 1
Software bit operations
Operations by I2C (master mode)
S: START condition, Sr: Repeated START condition, P: STOP condition,
A: ACK, A: NACK, Saddr/R: Slave address + R(1), Data n: 8-bit data
NO
YES
NO
YES
End
TXSTOP = 1
→
→
Data (N-1)
RXD[7:0]
Data N
Data N
A
P
RBFIF = 1
TXSTOP = 0
TXNACK = 0
STOPIF = 1
TXSTART = 1
→
RXD[7:0]
Data N
A
Sr
RBFIF = 1
TXSTART = 0
TXNACK = 0
STARTIF = 1
TBEIF = 1
TXSTART = 1
TXSTOP = 1
→
RXD[7:0]
Data N
A
P
S
RBFIF = 1
TXSTART = 0
TXNACK = 0
STARTIF = 1
TBEIF = 1
TXSTOP = 0
STOPIF = 1
Hardware bit operations
Operations by the external slave
Retry?
No
Write 1 to the I2CnCTL.TXSTOP bit
S1C17F13 TeChniCal Manual
YES
(Rev. 1.0)
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