Operations In Sram Mode - Epson S1C17F13 Technical Manual

3. Configure the following PIOMOD register bits:
- PIOMOD.PUL bit
- PIOMOD.GPIOMD bit
4. Set the following PIOCTL register bits:
- Set the PIOCTL.SFTRST bit to 1. (Execute software reset)
- Set the PIOCTL.MODEN bit to 1. (Enable PIO operations)
17.4.2

Operations in SRAM Mode

The PIO, which is placed into SRAM mode (PIOMOD.GPIOMD bit = 0), functions as an SRAM type parallel in-
terface.
Data write procedure
1. Write an address to be accessed and output data to the PIOWRDAT register.
- PIOWRDAT.PADDR[7:0] bits
- PIOWRDAT.PWDATA[7:0] bits
2. When outputting data successively, wait until the PIOSTAT.WBUSY bit goes to 0.
3. Repeat Steps 1 and 2 until the end of data output.
Data write operations
Writing an address/data to the PIOWRDAT register generates a trigger signal and it is sampled within one
CLK_PIO clock cycle. This starts a data write cycle.
After one clock cycle from the trigger sampling, PIO asserts the #PIOCE signal and outputs the address and
data from the PIOA[7:0] pins and the PIOD[7:0] pins, respectively. The PIOSTAT.WBUSY bit is also set to 1
(write cycle busy status).
PIO asserts the #PIOWR signal while the access cycle (one CLK_PIO clock cycle) after the setup cycle (one
CLK_PIO clock cycle).
PIO negates the #PIOCE signal and switches the PIOD[7:0] pin direction to input after the hold cycle (one
CLK_PIO clock cycle).
Finally, PIO clears the PIOSTAT.WBUSY bit to 0 (write cycle completed/idle status).
Trigger signal
CLK_PIO
PIOA[7:0]
PIOD[7:0]
PIOSTAT.WBUSY
Data read procedure
1. Write an address to be accessed to the PIOWRDAT.PADDR[7:0] bits.
2. Write 1 to the PIOCTL.RACC bit. (Data read trigger)
3. Wait until the PIOSTAT.RBUSY bit goes to 0.
4. Read the input data from the PIORDDAT.PRDATA[7:0] bits.
5. Repeat Steps 1 to 4 until the end of data input.
S1C17F13 TeChniCal Manual
(Rev. 1.0)
(Enable/disable pin pull-up)
(Select SRAM mode or GPIO mode)
(Address)
(Output data)
Address/data (W) → PIOWRDAT
Sampling & clear
#PIOCE
#PIOWR
State
Idle
Figure 17. 4.2.1 Data Write Timing
Seiko epson Corporation
PIOWRDAT.PADDR[7:0]
PIOWRDAT.PWDATA[7:0]
Setup Access Hold
17 Parallel Interface (PIO)
Idle
17-3