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21
Multiplier/Divider (COPRO)
21.1
Overview
COPRO is the coprocessor that provides multiplier/divider functions. The features of COPRO are listed below.
• Multiplication:
• Multiplication and accumulation (MAC): Supports signed MAC operations with overflow detection function.
• Division:
Figure 21.1.1 shows the COPRO configuration.
S1C17 Core
21.2
Operation Mode and Output Mode
COPRO operates according to the operation mode specified by the application program. As listed in Table 21.2.1,
COPRO supports nine operations.
The multiplication, division and MAC results are 32-bit data, therefore, the S1C17 Core cannot read them in one
access cycle. The output mode is provided to specify the high-order 16 bits or low-order 16 bits of the operation
results to be read from COPRO.
The operation and output modes can be specified with a 7-bit data by writing it to the mode setting register in CO-
PRO. Use a "ld.cw" instruction for this writing.
ld.cw
%rd,%rs
ld.cw
%rd,imm7
6
Output mode setting value
S1C17F13 TeChniCal Manual
(Rev. 1.0)
Supports signed/unsigned multiplications.
(16 bits × 16 bits = 32 bits)
Can be executed in 1 cycle.
(16 bits × 16 bits + 32 bits = 32 bits)
Can be executed in 1 cycle.
Supports signed/unsigned divisions.
(16 bits ÷ 16 bits = 16 bits with 16-bit residue)
Can be executed in 17 to 20 cycles.
COPRO
Argument 2
Argument 1
Selector
Coprocessor
output
Flag output
Figure 21.
1.1 COPRO Configuration
%rs[6:0] is written to the mode setting register. (%rd: not used)
imm7[6:0] is written to the mode setting register. (%rd: not used)
4
Figure 21.
2.1 Mode Setting Register
Seiko epson Corporation
Arithmetic unit
Operation
result
Operation result
register
3
Operation mode setting value
21 Multiplier/Divider (COPRO)
Mode setting
0
21-1
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