Port Input Register - Infineon Technologies TC1784 User Manual

Field Bits
0 [31:16] r
Note: Only Ports 0, 3, and 5 are 16-bit wide ports. The Pn_ESR registers of the other
ports have a reduced number of bits (see Pn_ESR register descriptions in the
corresponding port sections).
9.2.6

Port Input Register

The logic level of a GPIO pin can be read via the read-only port input register Pn_IN.
Reading the Pn_IN register allways returns the current logical value at the GPIO pin
independently whether the pin is selected as input or output.
Pn_IN (n=0-10)
Port n Input Register
31 30 29 28
15 14 13 12
P15 P14 P13 P12 P11 P10
rh rh rh rh
Field Bits
Px x
(x = 0-15)
0 [31:16] r
Note: The Pn_IN registers of the ports with less then 16 pins, have less than 16 Px bits
(see Pn_IN register descriptions in the corresponding port sections).
User´s Manual
Ports, V1.1
General Purpose I/O Ports and Peripheral I/O Lines (Ports)
Type Description
Reserved
Read as 0; should be written with 0.
(F000 0C24
27 26 25 24
11 10 9 8
P9 P8
rh rh rh rh
Type Description
rh Port n Input Bit x
This bit indicates the level at the input pin Pn.x.
0 The input level of Pn.x is 0.
B
1 The input level of Pn.x is 1.
B
Reserved
Read as 0.
9-20
+n*100 ) Reset Value: 0000 XXXX
H H
23 22 21
0
r
7 6 5
P7 P6 P5 P4
rh rh rh
TC1784
20 19 18 17
4 3 2 1
P3 P2 P1
rh rh rh rh
V1.1, 2011-05
H
16
0
P0
rh